公开(公告)号：AU2002306174A1

公开(公告)日：2003-12-31

申请号：AU2002306174

申请日：2002-06-14

Applicant: IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A ,  RADENS CARL J ,  WONG ROBERT C

IPC: H01L29/41 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/52 ,  H01L23/535 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A structure and method is disclosed for forming a buried interconnect (10) of an integrated circuit in a single crystal semiconductor layer (12) of a substrate. The buried interconnect is formed of a deposited conductor and has one or more vertical sidewalls (18) which contact a single crystal region of an electronic device (20) formed in the single crystal semiconductor layer.

公开(公告)号：DE112018005441B4

公开(公告)日：2022-12-22

申请号：DE112018005441

申请日：2018-09-21

Applicant: IBM

Inventor： EBRISH MONA ,  GLUSCHENKOV OLEG

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L29/161

Abstract: Struktur (5) zur Verringerung eines lateralen Reihenwiderstands für Transistoren, wobei die Struktur aufweist:ein leitfähiges Gate (16), welches über einem Halbleitersubstrat (10) ausgebildet und von diesem isoliert ist;Source- und/oder Drain-Zonen (26), die über dem Substrat (10) ausgebildet sind; undSource- und/oder Drain-Erweiterungszonen (22, 22`), die über dem Substrat (10) und direkt unterhalb entsprechender Source- und/oder Drain-Zonen (26) ausgebildet sind und mit diesen in Kontakt stehen,wobei die Source- und/oder Drain-Erweiterungszonen (22. 22`) aus SiGe sind, das mit einem ersten Element und einem zweiten Element legiert ist, wobei das erste Element so konfiguriert ist, dass es einen Gitterabstand des Materials, aus dem die Source- und/oder Drain-Erweiterungszonen (22, 22`) gebildet werden, erhöht, und das zweite Element so konfiguriert ist, dass es eine elektrische Leitfähigkeit der Source- und/oder Drain-Erweiterungszonen (22, 22`) erhöht,wobei das erste Element Zinn (Sn) und das zweite Element Gallium (Ga) ist, und wobei das Sn und das Ga in einer ihre chemische Löslichkeit übersteigenden Menge vorhanden ist.

公开(公告)号：AT551727T

公开(公告)日：2012-04-15

申请号：AT04702490

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER ,  DORIS BRUCE ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

Abstract: A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.

公开(公告)号：AT512465T

公开(公告)日：2011-06-15

申请号：AT04810633

申请日：2004-11-09

Applicant: IBM

Inventor： DORIS BRUCE ,  BELYANSKY MICHAEL ,  BOYD DIANE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8238

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

公开(公告)号：DE102004001099B4

公开(公告)日：2009-12-31

申请号：DE102004001099

申请日：2004-01-05

Applicant: QIMONDA AG ,  IBM

Inventor： BELYANSKY MICHAEL ,  GLUSCHENKOV OLEG ,  KNORR ANDREAS

IPC: H01L21/316 ,  C23C8/06 ,  C23C8/12 ,  C23C8/36 ,  H01L21/473 ,  H05H1/46

Abstract: A method of oxidizing a substrate having area of about 30,000 mm 2 or more. The surface is preferably comprised of silicon-containing materials, such as silicon, silicon germanium, silicon carbide, silicon nitride, and metal silicides. A mixture of oxygen-bearing gas and diluent gas normally non-reactive to oxygen, such as Ne, Ar, Kr, Xe, and/or Rn are ionized to create a plasma having an electron density of at least about 1 e12 cm -3 and containing ambient electrons having an average temperature greater than about 1 eV. The substrate surface is oxidized with energetic particles, comprising primarily atomic oxygen, created in the plasma to form an oxide film of substantially uniform thickness. The oxidation of the substrate takes place at a temperature below about 700° C., e.g., between about room temperature, 20° C., and about 500° C.

公开(公告)号：SG153032A1

公开(公告)日：2009-06-29

申请号：SG2008089690

申请日：2008-12-03

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES CORP ,  SAMSUNG ELECTRONICS CO LTD

Inventor： WOH LAI CHUNG ,  WEE TEO LEE ,  PING LIU JIN ,  GLUSCHENKOV OLEG ,  UTOMO HENRY K ,  MADAN ANITA ,  LOESING RAINER ,  JIN-PING HAN ,  YOON CHOI HYUNG

Abstract: An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.

公开(公告)号：DE10393309T5

公开(公告)日：2005-12-29

申请号：DE10393309

申请日：2003-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CABRAL CYRIL JR ,  IGGULDEN ROY C ,  MCSTAY IRENE LENNOX ,  CLEVENGER LAWRENCE A ,  WANG YUN YU ,  WONG KEITH KWONG HON ,  ROBL WERNER ,  GLUSCHENKOV OLEG ,  MALIK RAJEEV ,  SCHUTZ RONALD J

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78

Abstract: A conductive structure in an integrated circuit ( 12 ), and a method of forming the structure, is provided that includes a polysilicon layer ( 30 ), a thin layer containing titanium over the polysilicon, a tungsten nitride layer ( 34 ) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region ( 38 ) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer ( 30 ) and the tungsten layer ( 32 ), and provides low interface resistance between the tungsten layer and the polysilicon layer.

公开(公告)号：AU2003273328A8

公开(公告)日：2004-04-08

申请号：AU2003273328

申请日：2003-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE ,  SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78

Abstract: A conductive structure in an integrated circuit ( 12 ), and a method of forming the structure, is provided that includes a polysilicon layer ( 30 ), a thin layer containing titanium over the polysilicon, a tungsten nitride layer ( 34 ) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region ( 38 ) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer ( 30 ) and the tungsten layer ( 32 ), and provides low interface resistance between the tungsten layer and the polysilicon layer.

公开(公告)号：DE10246306A1

公开(公告)日：2003-04-30

申请号：DE10246306

申请日：2002-10-04

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHUDZIK MICHAEL ,  GLUSCHENKOV OLEG ,  JAMMY RAJARAO ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/316 ,  H01L21/321 ,  H01L21/8242 ,  H01G4/06

Abstract: An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

公开(公告)号：DE10244569A1

公开(公告)日：2003-04-24

申请号：DE10244569

申请日：2002-09-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT ,  WEYBRIGHT MARY

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336

Abstract: A semiconductor gate is capped with a pad oxide layer (20), which is bounded by one or more isolation trenches filled with silicon oxide. The pad oxide layer is thickened to a specified thickness to form a sacrificial oxide layer, then the sacrificial oxide layer is stripped and the semiconductor gate is capped with gate oxide layer. An Independent claim is also included for semiconductor structure.