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    GAP-TYPE CONDUCTIVE INTERCONNECT STRUCTURES IN SEMICONDUCTOR DEVICE
    41.
    发明申请
    GAP-TYPE CONDUCTIVE INTERCONNECT STRUCTURES IN SEMICONDUCTOR DEVICE 审中-公开
    半导体器件中的GAP型导电互连结构

    公开(公告)号：WO2005117085A3

    公开(公告)日：2006-10-12

    申请号：PCT/US2005018050

    申请日：2005-05-23

    Applicant: IBM ,  STAMPER ANTHONY K

    Inventor： STAMPER ANTHONY K

    IPC: H01L21/311 ,  H01L21/02 ,  H01L21/768

    CPC classification number: H01L21/7682 ,  H01L21/31116 ,  H01L21/76807 ,  H01L28/87

    Abstract: A method of forming a semiconductor device, and the device so formed. Depositing alternating layers of a first dielectric material (12a-f) and a second dielectric material (14a-f), wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature (22, 24) within the alternating layers of dielectric material. Selectively etching the alternating layers of dielectric material to remove at least a portion (26) of the first dielectric material in each layer having the first dielectric material and leaving the second dielectric material as essentially unetched.

    Abstract translation: 形成半导体器件的方法以及如此形成的器件。 沉积第一介电材料（12a-f）和第二介电材料（14a-f）的交替层，其中所述第一和第二介电材料可以以不同的速率被选择性地蚀刻。 在电介质材料的交替层内形成第一特征（22,24）。 选择性地蚀刻介电材料的交替层以去除具有第一电介质材料的每层中的第一介电材料的至少一部分（26），并使第二介电材料基本上未被蚀刻。

    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION
    43.
    发明申请
    REMOVAL OF ETCHING PROCESS RESIDUAL IN SEMICONDUCTOR FABRICATION 审中-公开
    在半导体制造中去除蚀刻工艺残留

    公开(公告)号：WO2008091923A3

    公开(公告)日：2009-12-30

    申请号：PCT/US2008051758

    申请日：2008-01-23

    Applicant: IBM ,  HERRIN RUSSELL T ,  LINDGREN PETER J ,  STAMPER ANTHONY K

    Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  STAMPER ANTHONY K

    IPC: C11D7/00

    CPC classification number: H01L23/5223 ,  H01L21/02063 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure and methods for forming the same. A semiconductor fabrication method includes steps of providing a structure. A structure incl udes (a) a dielectric layer, (b) a first electrically conductive region buried in the dielectric layer, wherein the first electrically conductive region comprises a first electrically conductive material, and (c) a second electrically conductive region buried in the dielectric layer, wherein the second electrically conductive region comprises a second electrically conductive material being different from the first electrically conductive material. The method further includes the steps of creating a first hole and a second hole in the dielectric layer resulting in the first and second electrically conductive regions being exposed to a surrounding ambient through the first and second holes, respectively. Then, the method further includes the steps of introducing a basic solvent to bottom walls and side walls of the first and second holes.

    Abstract translation: 半导体结构及其形成方法。 半导体制造方法包括提供结构的步骤。 一种结构包括（a）介电层，（b）掩埋在所述电介质层中的第一导电区域，其中所述第一导电区域包括第一导电材料，和（c）第二导电区域， 介电层，其中第二导电区域包括不同于第一导电材料的第二导电材料。 该方法还包括以下步骤：在电介质层中形成第一孔和第二孔，导致第一和第二导电区域分别通过第一孔和第二孔暴露于周围环境。 然后，该方法还包括将碱性溶剂引入第一孔和第二孔的底壁和侧壁的步骤。

    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME
    44.
    发明申请
    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 审中-公开
    通过VIAS的低电阻和电感及其制造方法

    公开(公告)号：WO2007084879A3

    公开(公告)日：2008-02-21

    申请号：PCT/US2007060544

    申请日：2007-01-15

    Applicant: IBM ,  ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    Inventor： ERTURK METE ,  GROVES ROBERT A ,  JOHNSON JEFFREY B ,  JOSEPH ALVIN J ,  LIU QIZHI ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    IPC: H01L21/00 ,  H01L21/302 ,  H01L21/306 ,  H01L21/44 ,  H01L21/77

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation (250) in a substrate (100), the substrate (100) having a frontside and an opposing backside; forming a first dielectric layer (105) on the frontside of the substrate (100); forming a trench (265C) in the first dielectric layer (105), the trench (265C) aligned over and within a perimeter of the dielectric isolation (250) and extending to the dielectric isolation (250); extending the trench (265C) formed in the first dielectric layer (1 05) through the dielectric isolation (250) and into the substrate (1 00)to a depth (Dl ) less than a thickness of the substrate (1 00); filling the trench (265C) and co-planarizing a top surface of the trench (265C) with a top surface of the first dielectric layer (1 05) to form an electrically conductive through via (270C); and thinning the substrate (100) from a backside of the substrate (100) to expose the through via (270C).

    Abstract translation: 背面接触结构及其制造方法。 该方法包括：在衬底（100）中形成绝缘隔离（250），所述衬底（100）具有前侧和相对的背面; 在所述基板（100）的前侧形成第一介电层（105）; 在所述第一电介质层（105）中形成沟槽（265C），所述沟槽（265C）在所述电介质隔离（250）的周边内并且在所述绝缘隔离（250）的周边内并且延伸到所述电介质隔离（250）; 将形成在第一电介质层（105）中的沟槽（265C）延伸通过电介质隔离（250）并延伸到衬底（100）中至小于衬底厚度（001）的深度（D1）。 填充沟槽（265C）并且将沟槽（265C）的顶表面与第一介电层（105）的顶表面共平面化以形成导电通孔（270C）; 以及从所述衬底（100）的背面使所述衬底（100）变薄以暴露所述通孔（270C）。

    Integrierte Halbleitereinheiten mit einkristallinem Träger, Verfahren zur Herstellung und Entwurfsstruktur
    47.
    发明专利
    Integrierte Halbleitereinheiten mit einkristallinem Träger, Verfahren zur Herstellung und Entwurfsstruktur 未知

    公开(公告)号：DE112012004719T5

    公开(公告)日：2014-08-07

    申请号：DE112012004719

    申请日：2012-08-14

    Applicant: IBM

    Inventor： HARAME DAVID L ,  STAMPER ANTHONY K

    IPC: H03H9/54

    Abstract: Es werden akustische Bulk-Wellen-Filter und/oder akustische Bulk-Resonatoren, die mit CMOS-Einheiten kombiniert sind, Verfahren zur Herstellung sowie eine Entwurfsstruktur bereitgestellt. Das Verfahren beinhaltet ein Bilden eines einkristallinen Trägers (18) aus einer Siliciumschicht (14) auf einem Isolator (12). Das Verfahren beinhaltet des Weiteren ein Bereitstellen einer Beschichtung aus einem Isolatormaterial (22) über dem einkristallinen Träger. Das Verfahren beinhaltet des Weiteren ein Bilden eines Durchkontakts (34a) durch das Isolatormaterial hindurch, wobei ein Wafer (10) freigelegt wird, der unter dem Isolator liegt. Das Isolatormaterial verbleibt über dem einkristallinen Träger. Das Verfahren beinhaltet des Weiteren ein Bereitstellen eines Opfermaterials (36) in dem Durchkontakt und über dem Isolatormaterial. Das Verfahren beinhaltet des Weiteren ein Bereitstellen einer Kappe (38) auf dem Opfermaterial. Das Verfahren beinhaltet des Weiteren ein Abführen des Opfermaterials und eines Anteils des Wafers unter dem einkristallinen Träger durch die Kappe hindurch, um einen oberen Hohlraum (42a) oberhalb des einkristallinen Trägers und einen unteren Hohlraum (42b) in dem Wafer unterhalb des einkristallinen Trägers zu bilden.

    Planar cavity MEMS and related structures, methods of manufacture and design structures
    48.
    发明专利
    Planar cavity MEMS and related structures, methods of manufacture and design structures 未知

    公开(公告)号：GB2494360B

    公开(公告)日：2013-09-18

    申请号：GB201300091

    申请日：2011-06-08

    Applicant: IBM

    Inventor： DUNBAR GEORGE A ,  HE ZHONG-XIANG ,  MURPHY WILLIAM J ,  STAMPER ANTHONY K ,  MALING JEFFREY C

    IPC: B81C1/00

    Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes patterning a wiring layer to form at least one fixed plate and forming a sacrificial material on the wiring layer. The method further includes forming an insulator layer of one or more films over the at least one fixed plate and exposed portions of an underlying substrate to prevent formation of a reaction product between the wiring layer and a sacrificial material. The method further includes forming at least one MEMS beam that is moveable over the at least one fixed plate. The method further includes venting or stripping of the sacrificial material to form at least a first cavity.

    A switchable interdigital transducer in a SAW filter
    49.
    发明专利
    A switchable interdigital transducer in a SAW filter 未知

    公开(公告)号：GB2499308A

    公开(公告)日：2013-08-14

    申请号：GB201300243

    申请日：2013-01-08

    Applicant: IBM

    Inventor： JAFFE MARK DAVID ,  ADKISSON JAMES WILLIAM ,  STAMPER ANTHONY K ,  WOLF RANDY LEE ,  CANDRA PANGLIJEN ,  GAMBINO JEFFERY P ,  DUNBAR THOMAS J

    IPC: H03H9/64 ,  H03H3/08 ,  H03H9/145

    Abstract: The fingers 22 of a movable electrode of an interdigital transducer (IDT) lie in a cavity above the piezoelectric layer 12 and are moved down to contact the layer 12, between the fingers 14 of a fixed electrode, by applying voltages to electrostatic actuator electrodes 16 or 24. Alternatively, the movable fingers 22 may be formed just above the layer 12 and the actuators used to move the fingers away from the layer 12 or to apply a downward pull-in contact force. The technique allows the switching into circuit of SAW filters without incurring the insertion loss caused by FET switches, or a reduction in Q factor. A SAW filter arrangement may be set to a desired frequency by activating or deactivating selected SAW filters.

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