公开(公告)号：DE10002374A1

公开(公告)日：2001-08-02

申请号：DE10002374

申请日：2000-01-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  BOEHM THOMAS ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C14/00 ,  G11C11/22 ,  G11C11/406

Abstract: The memory arrangement has a memory cell field (7) with a number of memory cells driven via word lines and bit lines and a refresh logic circuit (8) for refreshing the memory contents of the memory cell field. A comparator circuit (9) compares a characteristic parameter of at least one memory cell (10) with a reference value (VREF) and activates the refresh logic as required.

公开(公告)号：DE19926766A1

公开(公告)日：2000-12-21

申请号：DE19926766

申请日：1999-06-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER THOMAS ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG ,  ROEHR THOMAS ,  SCHINDLER GUENTHER ,  HARTNER WALTER ,  BOEHM THOMAS ,  WENDT HERMANN

IPC: H01L29/78

Abstract: According to the invention, two source/drain regions (121, 122) between which a channel region is arranged are provided for on a semiconductor substrate. On the surface of the channel region a gate dielectric (13) is positioned. Above the gate dielectric (13) a ferroelectric layer (14) and a gate electrode (15) are arranged. The ferroelectric layer (14) overlaps one of the source/drain regions (121). To change the polarization of the ferroelectric layer (14) a voltage can be applied between the gate electrode (15) and the overlapped source/drain region (121).

公开(公告)号：DE50105919D1

公开(公告)日：2005-05-19

申请号：DE50105919

申请日：2001-09-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: An integrated magnetoresistive semiconductor memory system, in which n memory cells that contain two magnetic layers each separated by a thin dielectric barrier, and associated word lines and bit lines that cross one another are vertically stacked in n layers. The system further contains a decoding circuit for selecting one of the n memory layers. The decoding circuit, on both ends of a word line or a bit line, is provided with one configuration each that contains n layer selecting transistors for selecting one of the n memory layers, and with a line selection transistor for selecting the respective horizontal word line or bit line on which a voltage is to be impressed.

公开(公告)号：DE59910447D1

公开(公告)日：2004-10-14

申请号：DE59910447

申请日：1999-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  BRAUN GEORG ,  MANYOKI ZOLTAN ,  ROEHR DR ,  BOEHM THOMAS

IPC: G11C8/00 ,  G11C8/10 ,  H03K19/084 ,  H03K19/094 ,  H03K19/23 ,  H03M5/16

Abstract: An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential.

公开(公告)号：DE50000869D1

公开(公告)日：2003-01-16

申请号：DE50000869

申请日：2000-03-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  BRAUN GEORG

IPC: G11C11/22 ,  G11C29/00 ,  G11C29/52

Abstract: Before a write and/or read access to one of the memory cells is carried out, a security information stored in a security memory cell is read out. If the security information is characterized by a first logic state an error signal is generated. If the read-out security information is characterized by a second logic state the memory cell is accessed and a write access is carried out to the security memory cell during which a new security information to be he stored having the second logic state is written to the cell.

公开(公告)号：DE10056830C2

公开(公告)日：2002-10-24

申请号：DE10056830

申请日：2000-11-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  G11C11/14

Abstract: An integrated magnetoresistive semiconductor memory system, in which n memory cells that contain two magnetic layers each separated by a thin dielectric barrier, and associated word lines and bit lines that cross one another are vertically stacked in n layers. The system further contains a decoding circuit for selecting one of the n memory layers. The decoding circuit, on both ends of a word line or a bit line, is provided with one configuration each that contains n layer selecting transistors for selecting one of the n memory layers, and with a line selection transistor for selecting the respective horizontal word line or bit line on which a voltage is to be impressed.

公开(公告)号：DE50000261D1

公开(公告)日：2002-08-08

申请号：DE50000261

申请日：2000-01-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  HOENIGSCHMID HEINZ ,  BOEHM THOMAS ,  ROEHR THOMAS ,  MANYOKI ZOLTAN

IPC: G11C11/408 ,  G11C7/06 ,  G11C7/10 ,  G11C11/22 ,  G11C11/407 ,  G11C11/409

Abstract: The integrated memory has m>1 bit lines that are connected to an input of a read-write amplifier via a switching element. Only one switching element is conductively connected for each read or write access. The memory is provided with a switching unit that influences read or write access occurring by way of the read-write amplifier and bit lines. The circuit unit is provided with an activation input. A column-end decoder has a first decoder stage and m second decoder stages. The outputs of the second decoder stages are connected to a control input for each of the switching elements. The output of the first decoder stage is connected to the activation input of the switching unit.

公开(公告)号：DE10047149A1

公开(公告)日：2002-04-18

申请号：DE10047149

申请日：2000-09-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  BOEHM THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/22 ,  H01L27/115 ,  H01L27/11502

Abstract: A chain-FRAM (CFRAM) includes a read-amplifier with bit-lines (BLt) connected to it, word-lines (WL) connected to the gates of selection transistors, a plate line (PLt) connected to the ends of the blocks of cells (Z) opposite the block-select transistors (BSt), complementary bit-lines (BLc) connected to the read-amplifier (SA), and complementary word-lines, complementary selection transistors, and complementary plate-lines (PLt). The bit-lines and the complementary bit-lines, and the memory cells (Z) and complementary memory cells connected to them, are arranged into two different memory cell matrices/fields (8,9), and the bit-line and the complementary bit-lines specifically extend in mutually opposite directions.

公开(公告)号：DE10032271A1

公开(公告)日：2002-01-24

申请号：DE10032271

申请日：2000-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two memory cell arrays, with the result that the area for the driver circuits can practically be halved. Therefore a space-saving architecture and a more efficient MRAM configuration is obtained.

公开(公告)号：DE10014385A1

公开(公告)日：2001-10-04

申请号：DE10014385

申请日：2000-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MANYOKI ZOLTAN ,  ESTERL ROBERT ,  BOEHM THOMAS ,  LAMMERS STEFAN

IPC: G05F3/24 ,  H01L23/58 ,  H01L27/085 ,  H03H11/00

Abstract: The voltage divider includes a first chain (A) comprising series-connected, n-type MOS transistors (N0-N4), of similar dimensions and similar gate-source voltages and which operate in the linear region. The voltage to be divided is applied to the ends of the chain, and the divided voltages are available at the respective source terminals. A second chain (B) of MOS transistors (P0-P4), complementary to the first transistors has the same dimensions and number as the first chain. The transistors of the first chain are connected to the transistors of the second chain. Each transistor chain (A,B) produces the gate-source bias voltage for the other transistors chain (B,A).