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    43.
    发明专利
    未知

    公开(公告)号：DE50105919D1

    公开(公告)日：2005-05-19

    申请号：DE50105919

    申请日：2001-09-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

    IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

    Abstract: An integrated magnetoresistive semiconductor memory system, in which n memory cells that contain two magnetic layers each separated by a thin dielectric barrier, and associated word lines and bit lines that cross one another are vertically stacked in n layers. The system further contains a decoding circuit for selecting one of the n memory layers. The decoding circuit, on both ends of a word line or a bit line, is provided with one configuration each that contains n layer selecting transistors for selecting one of the n memory layers, and with a line selection transistor for selecting the respective horizontal word line or bit line on which a voltage is to be impressed.

    2T2C SIGNAL MARGIN TEST MODE USING DIFFERENT PRE-CHARGE LEVELS FOR BL AND/BL
    44.
    发明专利
    2T2C SIGNAL MARGIN TEST MODE USING DIFFERENT PRE-CHARGE LEVELS FOR BL AND/BL 未知

    公开(公告)号：AU2003278684A1

    公开(公告)日：2004-06-15

    申请号：AU2003278684

    申请日：2003-11-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： JACOB MICHAEL ,  ROEHR THOMAS ,  WOHLFAHRT JOERG ,  JOACHIM HANS-OLIVER

    IPC: G11C29/50 ,  G11C29/00

    Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data The capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A potential is connected to the first bit line through a third transistor and changes a pre-charge signal level on the first bit line when the third transistor is turned on to reduce the differential read signal.

    45.
    发明专利
    未知

    公开(公告)号：DE10056830C2

    公开(公告)日：2002-10-24

    申请号：DE10056830

    申请日：2000-11-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

    IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  G11C11/14

    Abstract: An integrated magnetoresistive semiconductor memory system, in which n memory cells that contain two magnetic layers each separated by a thin dielectric barrier, and associated word lines and bit lines that cross one another are vertically stacked in n layers. The system further contains a decoding circuit for selecting one of the n memory layers. The decoding circuit, on both ends of a word line or a bit line, is provided with one configuration each that contains n layer selecting transistors for selecting one of the n memory layers, and with a line selection transistor for selecting the respective horizontal word line or bit line on which a voltage is to be impressed.

    46.
    发明专利
    未知

    公开(公告)号：DE50000261D1

    公开(公告)日：2002-08-08

    申请号：DE50000261

    申请日：2000-01-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BRAUN GEORG ,  HOENIGSCHMID HEINZ ,  BOEHM THOMAS ,  ROEHR THOMAS ,  MANYOKI ZOLTAN

    IPC: G11C11/408 ,  G11C7/06 ,  G11C7/10 ,  G11C11/22 ,  G11C11/407 ,  G11C11/409

    Abstract: The integrated memory has m>1 bit lines that are connected to an input of a read-write amplifier via a switching element. Only one switching element is conductively connected for each read or write access. The memory is provided with a switching unit that influences read or write access occurring by way of the read-write amplifier and bit lines. The circuit unit is provided with an activation input. A column-end decoder has a first decoder stage and m second decoder stages. The outputs of the second decoder stages are connected to a control input for each of the switching elements. The output of the first decoder stage is connected to the activation input of the switching unit.

    47.
    发明专利
    未知

    公开(公告)号：DE10053965A1

    公开(公告)日：2002-06-20

    申请号：DE10053965

    申请日：2000-10-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOGL DIETMAR ,  LAMMERS STEFAN ,  FREITAG MARTIN ,  ROEHR THOMAS

    IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

    Abstract: The arrangement has memory cells in a field in at least one plane at intersection points between word or programming lines and bit lines. Providing programming currents to word and bit lines corresponding to a selected cell causes stray magnetic fields in adjacent cells. The method involves feeding a compensation current to the adjacent cell word, programming, bit or special line to produce a compensation magnetic field countering the stray field. The MRAM arrangement has memory cells (11-13) in a memory cell field in at least one plane at intersection points between word lines (WL1) or programming lines and bit lines (BL1-BL3). Providing programming currents to word and bit lines corresponding to a selected cell causes stray magnetic fields in adjacent cells. The method involves feeding a compensation current to the word line or programming line or bit line or a special line of the adjacent cell(s) to produce a compensation magnetic field countering the stray field.

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