公开(公告)号：FR2853134B1

公开(公告)日：2005-07-01

申请号：FR0303647

申请日：2003-03-25

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： CARRIERE NICOLAS ,  SKOTNICKI THOMAS ,  TAVEL BRICE

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49

Abstract: The production of a metal grid of a transistor comprises a total siliconisation of the grid region. The siliconisation phase comprises: (a) the formation from a first metal of a first metal silicide on a first zone, whilst the second zone is protected by a hard masking layer; (b) the removal of the mask; (c) the formation from a second metal of a second metal silicide on the second zone, whilst the first metal silicide is protected by the second metal; and (d) the removal of the second metal. An independent claim is also included for an integrated circuit incorporating at least one transistor produced by this method.

公开(公告)号：FR2853134A1

公开(公告)日：2004-10-01

申请号：FR0303647

申请日：2003-03-25

Applicant: ST MICROELECTRONICS SA ,  COMMISSARIAT ENERGIE ATOMIQUE

Inventor： CARRIERE NICOLAS ,  SKOTNICKI THOMAS ,  TAVEL BRICE

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49

Abstract: The production of a metal grid of a transistor comprises a total siliconisation of the grid region. The siliconisation phase comprises: (a) the formation from a first metal of a first metal silicide on a first zone, whilst the second zone is protected by a hard masking layer; (b) the removal of the mask; (c) the formation from a second metal of a second metal silicide on the second zone, whilst the first metal silicide is protected by the second metal; and (d) the removal of the second metal. An independent claim is also included for an integrated circuit incorporating at least one transistor produced by this method.

公开(公告)号：FR2823009B1

公开(公告)日：2004-07-09

申请号：FR0104436

申请日：2001-04-02

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JOSSE EMMANUEL

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: The vertical transistor includes, on a semiconductor substrate, a vertical pillar 5 having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layer 7 situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first region 800 resting on the gate dielectric layer 7 and a second region 90 facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities 14S, 14D.

公开(公告)号：FR2846795A1

公开(公告)日：2004-05-07

申请号：FR0213838

申请日：2002-11-05

Applicant: ST MICROELECTRONICS SA

Inventor： MAZOYER PASCALE ,  VILLARET ALEXANDRE ,  SKOTNICKI THOMAS

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A integrated memory circuit comprises at least one memory cell formed from a single transistor of which the gate (GR) possesses a lower surface insulated from the channel region (RC) by an insulation layer (CIS) incorporating a succession of potential pits (ND) essentially arranged at a distance from the gate and the channel region in a plane essentially parallel to the lower surface of the gate and these potential pits are able to contain an electric charge confined in the plane and displaceable on command in the plane towards a first confinement region close to the source region (RS) or towards a second confinement region close to the drain region (RD), in a manner to define two memory states for the cell. Independent claims are also included for: (a) a method for the memorisation of binary data in the memory cell of this integrated memory circuit; (b) a method for the manufacture of this integrated memory circuit.

公开(公告)号：FR2839202A1

公开(公告)日：2003-10-31

申请号：FR0205286

申请日：2002-04-26

Applicant: ST MICROELECTRONICS SA

Inventor： MENUT OLIVIER ,  JAOUEN HERVE ,  BOUCHE GUILLAUME ,  SKOTNICKI THOMAS

IPC: H01L21/28 ,  H01L21/761 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762

Abstract: An assembly of MOS transistors with a minimal dimension of less than 0.1 mum comprises a silicon substrate (1) of which the upper surface is plane and with each active zone delimited by an insulating layer (25) deposited over the upper surface of the substrate. The active part (28) of the grid of each MOS transistor is formed with a conducting double layer, the lower layer having the same thickness as the insulating layer and the upper layer extending on the insulating layer to form a head of the grid (29). An Independent claim is also included for a method for the fabrication of this assembly of MOS transistors.

公开(公告)号：FR2838866A1

公开(公告)日：2003-10-24

申请号：FR0205073

申请日：2002-04-23

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  LEVERD FRANCOIS ,  SKOTNICKI THOMAS

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/68 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L51/00 ,  H01L51/40 ,  H01L21/70 ,  H01L27/108

Abstract: Fabrication of an integrated electronic component comprises: producing an initial structure (SI) incorporating volumes of respective materials forming a definite pattern (M) on a first substrate; transferring the pattern to a second substrate (200); and producing, on the second substrate surface, an additional structure by using the volumes of the materials of the pattern as alignment markers. Fabrication of an integrated electronic component comprises: (a) producing, on the surface of a first substrate (100), an initial structure (SI) incorporating volumes of respective materials, at least part of the volumes forming a definite pattern (M); (b) transferring at least a part of the initial structure (SI) comprising the pattern of the first substrate (100) to a second substrate (200); and (c) producing, on the surface of the second substrate (200), an additional structure by using at least some of the volumes of the materials of the pattern (M) as alignment markers. Independent claims are given for: (i) an integrated electronic component obtained by the invented process; and (ii) an electronic device comprising a transistor, or a diode, or a dynamic random access memory (DRAM) element.

公开(公告)号：FR2823010B1

公开(公告)日：2003-08-15

申请号：FR0104437

申请日：2001-04-02

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JOSSE EMMANUEL

IPC: H01L21/336 ,  H01L29/165 ,  H01L29/78

Abstract: The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL 1 ,PL 2 extending between the source and drain regions, and forming two very fine pillars.

公开(公告)号：FR2823032B1

公开(公告)日：2003-07-11

申请号：FR0104510

申请日：2001-04-03

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  DUTARTRE DIDIER ,  RIBOT PASCAL

IPC: H03H3/00 ,  H03H9/24 ,  H03H9/00

Abstract: A resonator formed by the steps of defining an active single-crystal silicon layer delimited by a buried insulator layer, depositing a silicon-germanium layer by a selective epitaxy method so that the silicon-germanium layer grows above the active single-crystal silicon area, depositing by a non-selective epitaxy method a silicon layer and etching it according to a desired contour, and removing the silicon-germanium by a selective etching with respect to the silicon and to the insulator.

公开(公告)号：FR2818012A1

公开(公告)日：2002-06-14

申请号：FR0016174

申请日：2000-12-12

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  MONFRAY STEPHANE ,  HAOND MICHEL

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/80 ,  H01L27/105

Abstract: An integrated memory semiconductor device comprises at least one integrated structure of point-memory, incorporating a semiconducting zone of quantum pits (6) buried in the substrate (1) of the structure and arranged under the insulated grid (7) of a transistor, and a polarization means (16) for polarizing the structure in a manner that allows the charging or discharging of charges in the quantum pits or from the quantum pits.

公开(公告)号：FR2801970B1

公开(公告)日：2002-02-15

申请号：FR9915410

申请日：1999-12-07

Applicant: ST MICROELECTRONICS SA

Inventor： JAOUEN HERVE ,  SKOTNICKI THOMAS ,  JURCZAK MALGORZATA

IPC: G01D5/242 ,  G01L9/00 ,  G10K9/13 ,  G01D5/241 ,  H01L43/12

Abstract: A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.