公开(公告)号：JP2618615B2

公开(公告)日：1997-06-11

申请号：JP15598395

申请日：1995-06-22

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

公开(公告)号：JPH09129722A

公开(公告)日：1997-05-16

申请号：JP26699796

申请日：1996-10-08

Applicant: CONS RIC MICROELETTRONICA

Inventor： FRANCO GIOVANNI ,  CAMALLERI CATENO MARCO ,  FRISINA FERRUCCIO

IPC: H01L21/761 ,  H01L21/225 ,  H01L21/265 ,  H01L29/06

Abstract: PROBLEM TO BE SOLVED: To provide an electric power device wherein high yield efficiency is obtained with low ion implantation energy and provided with a deep edge ring by, with the use of a boron and Al as a dopant, forming a deep ring at the same time for the main body of a device in a single thermal process, and further, an oxide layer used during Al ion implantation. SOLUTION: On a heavily doped N type substrate 10, a slightly doped N type epitaxial layer 20 is grown, further, over the upper part of the epitaxial layer 20, an oxide 30 is grown. By photo-etching, an main body is exposed itself in an area 30, and boron 40 is implanted for a p are 42 to be generated. Then, oxide etching is performed, the area for Al ion implantation is made exposed, thus an Al ring is configured. By masking the main body area with a photosensitive material layer, an Al ion 60 is implanted. Then, through a single thermal diffusion process, P /N joint 80 formed through formation of a thermal oxide layer 70 and boron, and one or more P /N joints 90 formed by Al are formed at the same time.

公开(公告)号：JPH0969760A

公开(公告)日：1997-03-11

申请号：JP7435096

申请日：1996-03-28

Applicant: CONS RIC MICROELETTRONICA ,  SGS THOMSON MICROELECTRONICS

Inventor： FURANCHIESUKO PURUBUIRENTEI ,  RITSUKARUDO URUSHIINO ,  ROBERUTO GARIBORUDEI

IPC: H03F3/45 ,  H03K3/011 ,  H03K3/0231 ,  H03K3/354 ,  H03K4/06 ,  H03K19/0948

Abstract: PROBLEM TO BE SOLVED: To provide an oscillation circuit generating an oscillation electric signal which is not easily affected by supply voltage and a temperature. SOLUTION: A capacitor C, a charge circuit CCA and a control circuit CCO are provided. The charge circuit CCA contains a first current generation device GEN1 and a second current generation device GEN2, which have first and second current values and respectively opposite directions, and switch means SW1 and SW2 designed in such a way that the generation devices GEN1 and GEN2 are connected to the capacitor C. The control circuit CCO has voltage input connected to the capacitor C and output connected to the control inputs of the switch means SW1 and SW2 and contains a comparator containing a hysteresis having a lower-side threshold and an upper-side threshold.

公开(公告)号：JPH08306794A

公开(公告)日：1996-11-22

申请号：JP9344496

申请日：1996-03-22

Applicant: CONS RIC MICROELETTRONICA

Inventor： NATAARE AIERO ,  BUITSUTO GURATSUIAANO

IPC: H01L27/06 ,  H01L21/8222 ,  H01L27/02 ,  H03K17/735

Abstract: PROBLEM TO BE SOLVED: To ensure a timely response when the voltage of an isolated region clamped by a switch is rapidly changed by maintaining the isolated region with a reference potential, and instructing the opening of the switch. SOLUTION: When the potential of a region 1 (SUB) is rapidly dropped to a ground potential by capacity coupling, the potential of an isolated region 2 (ISO) is dragged toward a negative voltage value. The dynamic potential movement of the region 2 is detected by a comparator COMP beyond a reference voltage clamped by a switch T, and the switch T is opened by changing the state. The region 2 is turned into a high impedance state against a floating or ground node according to the opening of the switch T, and as a result, the region potential is turned into a free state by capacitive coupling C1 and C2, and the decreased voltage of the substrate region 1 is tracked by presenting a negative voltage value. Thus, the region 2 can be biased to the potential presented by the substrate region 1, and allowed to stay with a negative potential.

公开(公告)号：JPH08305575A

公开(公告)日：1996-11-22

申请号：JP7221496

申请日：1996-03-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： FURANCHIESUKO PATSUPARARUDO ,  BINCHIENTSUO MATORANGA ,  DABIDE TESHI ,  DARIO DEI BETSURA

IPC: G06F9/44 ,  G06F7/48 ,  G06F7/499 ,  G06N7/02 ,  G06N7/04

Abstract: PROBLEM TO BE SOLVED: To provide a method for storing a membership function for easily and economically deciding the crossing of the membership function with an input. SOLUTION: This method for storing a membership function includes the storing of a position CV in an universe of discourse UdD of the vertex of a triangle normalizing the membership function, and the storing of a first distance LVD between the cross point of the left side of the triangle with the axis of the universe of discourse and the position CV of the vertex. Moreover, this method includes the storing of a second distance RVD between the cross point of the right side of the triangle with the axis of the universe of discourse and the position CV of the vertex. Moreover, in a circuit which calculates the assignment of the data of the antecedent part of a fuzzy rule, an input variable can be made fuzzy by using a geometrical ratio generated among the similar corresponding sides of the triangle normalized by the position of an input value in the universe of discourse.

公开(公告)号：JPH08279737A

公开(公告)日：1996-10-22

申请号：JP29860695

申请日：1995-11-16

Applicant: CONS RIC MICROELETTRONICA ,  SGS THOMSON MICROELECTRONICS

Inventor： PAORO KORETSUTEI ,  GUREGORIO BONTENPO ,  FURANCHIESUKO PURUBUIRENTEI ,  ROBERUTO GARIBORUDEI

IPC: H01L27/04 ,  G05F1/573 ,  H01L21/822 ,  H01L29/78 ,  H02H7/00 ,  H03K17/08

Abstract: PROBLEM TO BE SOLVED: To provide a simple and correct method for protecting a power transistor(TR). SOLUTION: The method is provided with a process where a 1st electric signal S1 proportional substantially to a current flowing to a path D-S is generated, a process where a 2nd electric signal S2 proportional substantially to a voltage across the path D-S is generated, a process where the 1st signal S1 and the 2nd signal S2 are multiplied to generate an electric generating signal PS, a process where the electric generating signal PS is compared with an electric reference signal RS to generate an electric difference signal DS, and a process where the electric difference signal DS is used to drive a control terminal G so that the electric generating signal PS is smaller than the reference signal RS.

公开(公告)号：JPH08274183A

公开(公告)日：1996-10-18

申请号：JP28050295

申请日：1995-10-27

Applicant: CONS RIC MICROELETTRONICA

Inventor： JIYOBUANNA KATSUCHIOORA ,  SARUBUATOORE REONARUDEI ,  JIYANPIERO MONTARUBAANO

IPC: H01L21/8234 ,  H01L27/06 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To remove a layer containing the existence of a parasitic transistor which is not desirable with former constitution, by providing at least one N channel-type MOS transistor stored in a well which is directly brought into contact with an isolation well for a control circuit for semiconductor device, which is formed on a substrate where a first conductivity type dopant is doped. SOLUTION: An integrated circuit is provided with a first epitaxial layer 2 which is grown on a substrate 1 and to which a first conductivity type dopant is doped and the isolation well to which a second conductivity type dopant is doped. The control circuit is provided with at least a first control transistor M1 to which a second conductivity type dopant is doped and which is formed in a first well 8 formed in the isolation well.

公开(公告)号：JPH08139080A

公开(公告)日：1996-05-31

申请号：JP24610495

申请日：1995-09-25

Applicant: CONS RIC MICROELETTRONICA

Inventor： SHIRINO RAPISARUDA

IPC: C30B33/12 ,  C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method for etching a cobalt silicide layer for prescribing small shape dimensions. SOLUTION: In a method for etching a cobalt silicide layer 15, that is superposed on a polysilicon layer 14 formed on a silicon substrate 12 and is selectively covered with a mask material 16, the cobalt silicide layer 15 is exposed to a pressure stipulated to a gas nitrogen flow, a gas nitrogen is ionized by using a prescribed power, and a plasma for selectively eliminating the cobalt silicide layer 15 is formed.

公开(公告)号：JPH08111453A

公开(公告)日：1996-04-30

申请号：JP24327195

申请日：1995-09-21

Applicant: CONS RIC MICROELETTRONICA

Inventor： SARUBATOORE YUUGO KANPISAANO ,  BIITO RAINEERI

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/316 ,  H01L21/762 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To form a silicon oxide buried layer in a silicon wafer by a method, wherein a recess is formed in the silicon wafer, and light ions are injected at more shallow depth to form air bubbles, and the light ions are evaporated, and a cavity remains in a place of air bubbles for oxidizing the cavity via the recess. SOLUTION: If helium ions 3 are injected into the entire surface 2 of a silicon wafer 1, helium air bubbles 4 are formed at an average permeation depth of the ions 3. If the silicon wafer 1 is heated at a temperature of 700 deg.C or higher, helium diffuses to the surface 2 and a buried layer which is an empty cavity remains in a place of air bubbles 4. A recess or groove 5 is formed, so that its depth is deeper than the depth that the cavity 4 is installed and is divided into an upper portion 6a and a lower portion 6b. If the silicon wafer 1 is heated in a furnace at a dense oxygen concentration, the buried layer containing the cavity 4 is uniformly oxidized and a buried layer 7 of a silicon oxide can be formed in the silicon wafer 1.

公开(公告)号：JPH0866089A

公开(公告)日：1996-03-08

申请号：JP16242195

申请日：1995-06-28

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： GIUSETSUPE DANJIERO ,  RINARUDO PORUTSUTSUI ,  MATEO RO PURESUTEI

IPC: G05B13/02 ,  G05D13/62 ,  G05F1/10 ,  H02P23/00 ,  H02P27/06 ,  H02P7/63 ,  H02P5/00 ,  H02P5/41

Abstract: PURPOSE: To improve performance of an applied-voltage fuzzy control process and a usual control system by applying fuzzy control to velocity errors, differen tial coefficient of the velocity error and electric power errors, in order to gener ate the values of a pulse and a voltage which are proper for driving an electric motor. CONSTITUTION: A signal Wref , indicating a reference velocity, is sent to a comparison node 11. The node 11 also receives a signal W indicating a velocity which drives an AC motor. The node 11 is proper for generating a difference Wref -W, i.e., an error EW. The error signal EW is sent to a fuzzy controller 13. At the same time, the error signal EW is sent to a differential circuit 12, which is appropriate for generating a differential coefficient dEW/dt of the error signal EW. The differential coefficient deW/dt is sent to the fuzzy controller 13. A node 16 is appropriate for generating an electric power error signal EP of the fuzzy controller 13.