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    TRACE ANYWHERE INTERCONNECT
    52.
    发明申请
    TRACE ANYWHERE INTERCONNECT 审中-公开
    跟踪任何互连

    公开(公告)号：WO2017039790A1

    公开(公告)日：2017-03-09

    申请号：PCT/US2016/038687

    申请日：2016-06-22

    Applicant: R&D CIRCUITS, INC.

    Inventor： WARWICK, Thomas, P. ,  TURPUSEEMA, Dhananjaya ,  RUSSELL, James, V.

    IPC: H01R12/00 ,  B33Y80/00 ,  H01R12/14 ,  H01R13/02 ,  H05K1/14 ,  H05K3/36 ,  H01L23/522 ,  H01L23/535

    CPC classification number: H01R12/52 ,  H01L23/522 ,  H01L23/535 ,  H05K1/185 ,  H05K3/4046 ,  H05K2201/09118 ,  H05K2201/10287

    Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side

    Abstract translation: 本发明提供了用于在两个或更多个并联电路平面上的离散点之间形成三维布线的电介质线的方法和结构。 导线可以在三维空间中自由布线，以在两个或多个并联电路平面上的两个任意定义的点之间创建最有效的路由。 将这些三维电介质线的外表面金属化，将离散导线电耦合到它们各自的离散接触点。 这些线中的两个或更多个可以彼此紧密接触，彼此电耦合以及两个或更多个离散的接触垫。 这些电耦合接触焊盘可以在结构的相对侧或同一侧上，并且所形成的金属化导线可以源于一侧并且终止于另一侧或从相同侧产生并终止

    A STRUCTURE AND IMPLEMENTATION METHOD FOR IMPLEMENTING AN EMBEDDED SERIAL DATA TEST LOOPBACK, RESIDING DIRECTLY UNDER THE DEVICE UNDER TEST WITHIN A PRINTED CIRCUIT BOARD
    53.
    发明申请
    A STRUCTURE AND IMPLEMENTATION METHOD FOR IMPLEMENTING AN EMBEDDED SERIAL DATA TEST LOOPBACK, RESIDING DIRECTLY UNDER THE DEVICE UNDER TEST WITHIN A PRINTED CIRCUIT BOARD 审中-公开
    一种用于实现嵌入式串行数据测试环路的结构和实现方法，在打印机电路板内的测试设备下直接保留

    公开(公告)号：WO2016033146A1

    公开(公告)日：2016-03-03

    申请号：PCT/US2015/046870

    申请日：2015-08-26

    Applicant: R&D CIRCUITS, INC

    Inventor： WARWICK, Thomas P. ,  RUSSELL, James V.

    IPC: G01R31/303

    CPC classification number: H04L1/243 ,  G01R31/2851 ,  G01R31/31716 ,  G01R31/31937 ,  H04L1/205 ,  H04L41/24 ,  H04L43/50 ,  H05K1/0231 ,  H05K1/185 ,  H05K2201/10015

    Abstract: A method and a structure with multiple implementations is provided that depends on the specific need, for placing (embedding) a serial ioopback circuit of known design in a printed circuit board directly beneath the device under test. Micro- vias and traces connect components including transmitter components (TX) and receiver components (RX) that are formed into a Ioopback circuit for connection to a device under test (DUT). The connection is accomplished by a coupling capacitor with a shortest possible electrical length approximating a straight line between said components and said DUT and said distance is a length of said short straight line times a square root of 2 so that said receiver components are beneath the DUT.

    Abstract translation: 提供了具有多个实现的方法和结构，其取决于具体需要，将已知设计的串行回波电路放置（嵌入）在正在被测器件正下方的印刷电路板中。 微通道和迹线连接组件，包括形成为Ioopback电路的发射器组件（TX）和接收器组件（RX），用于连接到被测设备（DUT）。 该连接由耦合电容器实现，其具有近似于所述部件和所述DUT之间的直线的最短电长度，并且所述距离是所述短直线的长度乘以2的平方根，使得所述接收器部件在DUT下方 。

    METHOD AND STRUCTURE FOR FORMING CONTACT PADS ON A PRINTED CIRCUIT BOARD USING ZERO UNDER- CUT TECHNOLOGY
    54.
    发明申请
    METHOD AND STRUCTURE FOR FORMING CONTACT PADS ON A PRINTED CIRCUIT BOARD USING ZERO UNDER- CUT TECHNOLOGY 审中-公开
    使用零切割技术在印刷电路板上形成接触垫的方法和结构

    公开(公告)号：WO2014039072A1

    公开(公告)日：2014-03-13

    申请号：PCT/US2013/000185

    申请日：2013-08-09

    Applicant: R&D CIRCUITS, INC.

    IPC: H05K3/06 ,  H05K1/02 ,  H01L21/02

    CPC classification number: H05K3/425 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/243 ,  H05K3/4007 ,  H05K3/427 ,  H05K2201/0959 ,  Y10T29/49156

    Abstract: A method and an apparatus for forming a contact pad on a printed circuit board over a filled plate via or blind in which an additional metallic or a non metallic coating is applied to a final surface finished plate which encapsulates the side walls of the wear resistant surface plate, and also covers the side walls of the metal layer plated onto the filled via and the wrap around plated metal which was plated in the via and onto the surface of the base metal to the extents of the pad geometry. This prevents subsequent undermining through the etching process and ensuring the integrity and reliability of the vias' electrical connection when an underlying base metal such as but not limited to copper and the surface plated metal are formed when plating metal in the via and consequently onto the surface.

    Abstract translation: 一种用于在印刷电路板上形成接触焊盘的方法和装置，该印刷电路板在填充板通孔或盲孔上，其中附加的金属或非金属涂层施加到封装耐磨表面的侧壁的最终表面成品板 并且还覆盖镀在填充的通孔上的金属层的侧壁和镀在金属上的包裹物，其镀覆在基底金属的通孔中并达到基底金属的表面，达到垫几何形状的范围。 这防止了当通过通孔电镀金属并因此到达表面时形成下面的基底金属（例如但不限于铜）和表面电镀金属时，通过蚀刻工艺的后续破坏并确保通孔的电连接的完整性和可靠性 。

    SYSTEM AND METHOD FOR DETECTING DEFECTIVE BACK DRILLS IN PRINTED CIRCUIT BOARDS
    58.
    发明申请
    SYSTEM AND METHOD FOR DETECTING DEFECTIVE BACK DRILLS IN PRINTED CIRCUIT BOARDS 审中-公开

    公开(公告)号：WO2022174021A1

    公开(公告)日：2022-08-18

    申请号：PCT/US2022/016090

    申请日：2022-02-11

    Applicant: R&D CIRCUITS, INC.

    Inventor： THOMPSON, Donald, Eric ,  SMITH, Thomas

    IPC: H05K3/00

    Abstract: The present invention provides a method for detecting failed back-drills in PCBs in the process of fabricating a PCB so that the failed back-drill can be screened out or repaired. The present invention accomplishes this by adding a short to ground connection for every back- drill via that will be cut when the back-drill removes the via stub. If the back-drill is bad or failed the short to ground will fail the subsequent electrical tests. The PCB can be repaired by re- drilling the hole or via. The present invention allows for detecting failed back-drills with easy detection in the manufacturing stage using standard equipment and test procedures. This process creates a simple pass-fail measurement that uses an existing common test process to catch failed back drills in the PCB fabrication facility. This allows for easy and cost- effective repair and guarantees back-drill failures do not pass into the field.

    METHOD AND STRUCTURE FOR A 3D WIRE BLOCK
    59.
    发明申请
    METHOD AND STRUCTURE FOR A 3D WIRE BLOCK 审中-公开
    一种3D线块的方法和结构

    公开(公告)号：WO2018044788A1

    公开(公告)日：2018-03-08

    申请号：PCT/US2017/048885

    申请日：2017-08-28

    Applicant: R&D CIRCUITS, INC. ,  THOMPSON, Donald, Eric ,  CANTAIORE, Cosirno

    Inventor： THOMPSON, Donald, Eric ,  CANTAIORE, Cosirno

    IPC: B29C64/153 ,  H01R12/14 ,  H01R13/40 ,  H05K1/14 ,  H05K3/36

    Abstract: The present invention provides for a structure and a mechanism by which by utilising additive manufacturing processes electrical connections are created that connect the top and bottom of a block in a customizable pattern. Specifically connection points can be created on the surface of the block and route them to alternate locations transforming the original pattern to a smaller, larger, or alternate pattern.

    Abstract translation: 本发明提供了一种结构和机构，通过利用增材制造工艺，建立了以可定制图案连接块的顶部和底部的电连接。 具体来说，可以在块的表面创建连接点，并将它们路由到其他位置，将原始模式转换为更小，更大或交替的模式。

    A STRUCTURE FOR ACCEPTING A COMPONENT FOR AN EMBEDDED COMPONENT PRINTED CIRCUIT BOARD
    60.
    发明申请
    A STRUCTURE FOR ACCEPTING A COMPONENT FOR AN EMBEDDED COMPONENT PRINTED CIRCUIT BOARD 审中-公开
    嵌入式组件印刷电路板组件的结构

    公开(公告)号：WO2015168370A1

    公开(公告)日：2015-11-05

    申请号：PCT/US2015/028453

    申请日：2015-04-30

    Applicant: R&D CIRCUITS, INC

    Inventor： TURPUSEEMA, Dhanonjaya ,  WARWICK, Thomas, P. ,  SMITH, Thomas ,  RUSSELL, James, V.

    IPC: H05K3/30 ,  H05K3/46 ,  H05K3/40 ,  G06K19/077 ,  H05K1/18

    CPC classification number: H05K1/188 ,  H05K1/144 ,  H05K1/183 ,  H05K1/186 ,  H05K3/0026 ,  H05K3/0094 ,  H05K3/321 ,  H05K3/366 ,  H05K3/4655 ,  H05K3/4679 ,  H05K2201/032 ,  H05K2201/0355 ,  H05K2201/042 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09545 ,  H05K2201/09572 ,  H05K2203/0485 ,  H05K2203/063 ,  H05K2203/11 ,  Y10T29/49128 ,  Y10T29/4914

    Abstract: A method and electrical interconnect structure internal to a printed circuit board for the purposes of creating a reliable, high performing connection method between embedded component terminals, signal traces and or power/ground planes which may occupy the same vertical space as the embedded components, such as a capacitor or resistor. Further easing the assembly and reliability through the manufacturing process of said embedded component structures. In one structure castellated drilled, plated vias connect the trace or plane within the printed circuit board to the electrical terminals of the embedded component using a permanent and highly conductive attach material. In another structure, the trace or plane connect by selective side-wall plating, which surrounds the electrical terminal of the component This structure also uses a permanent and highly conductive attach material to electrically connect the component terminal to the plated side-wall and in a final embodiment the terminals are connected through a conductive attach material through a via in the z axis to a conductive pad.

    Abstract translation: 印刷电路板内部的方法和电互连结构，用于在嵌入式组件端子，信号迹线和/或电源/接地平面之间建立可靠的，高性能的连接方法，其可能占据与嵌入式组件相同的垂直空间，例如 作为电容器或电阻器。 通过所述嵌入式组件结构的制造过程进一步减轻组装和可靠性。 在一种结构化的钻孔中，电镀通孔使用永久且高度导电的附着材料将印刷电路板中的迹线或平面连接到嵌入式部件的电气端子。 在另一种结构中，轨迹或平面通过选择性侧壁电镀连接，其围绕部件的电端子。该结构还使用永久且高度导电的附着材料将部件端子电连接到电镀侧壁 最终实施例中，端子通过导电附着材料通过z轴中的通孔连接到导电垫。

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