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    A COMMUNICATION LINE SCANNING DEVICE FOR A COMMUNICATION CONTROLLER
    51.
    发明专利
    A COMMUNICATION LINE SCANNING DEVICE FOR A COMMUNICATION CONTROLLER 未知

    公开(公告)号：AU558173B2

    公开(公告)日：1987-01-22

    申请号：AU8979282

    申请日：1982-10-26

    Applicant: IBM

    Inventor： BREZZO BERNARD ,  CALVIGNAC JEAN ,  MASCLET ANDRE ,  SANCHE JEAN-PIERRE

    IPC: H04L69/14 ,  G06F13/00 ,  G06F13/38 ,  G06F3/04 ,  H04L11/20

    Abstract: A line scanning device which operates under the control of a microprocessor connected to a control memory in which a memory location area is assigned to each line is provided for a line adapter in a communication controller for receiving or sending message bits in series from or to terminals connected to the lines using any protocols. It comprises a first store which includes a first and a second memories, an area being assigned to each line in each of the memories which can be read and written in the same time and a second store which includes a single memory in which a storage location area is assigned to each line. These stores are addressed by a control and address unit which includes first and second address counters under the control of an elementary time counter, the first counter outputting the address information relating to the first store during time t provided for scanning a line, and the second counter outputting the address information relative to the second store during time nt, n being at least equal to 4, and control circuitry receiving said address information and the elementary time information for providing at the outputs of the control and address unit, memory address and read/write control information at times selected during the scanning period and sequentially, the addresses of the present lines which are scanned.

    54.
    发明专利
    未知

    公开(公告)号：DE602006007827D1

    公开(公告)日：2009-08-27

    申请号：DE602006007827

    申请日：2006-03-15

    Applicant: IBM

    Inventor： BASSO CLAUDE ,  CALVIGNAC JEAN ,  CHANG CHIH-JEN ,  DAMON PHILIPPE ,  VAIDHYANATHAN NATARAJAN ,  VERPLANKEN FABRICE ,  VERRILLI COLIN BEATON

    IPC: H04L29/06

    Abstract: A method for reducing latency in a host Ethernet adapter (HEA) includes the following. First, the HEA receives a packet with an internet protocol (IP) header and data in the HEA. The HEA parses a connection identifier from the IP header and accesses a negative cache in the HEA to determine if the connection identifier is not in a memory external to the HEA. The HEA applies a default treatment to the packet if the connection identifier is not in the memory, thereby reducing latency by decreasing access to the memory.

    56.
    发明专利
    未知

    公开(公告)号：DE68926740D1

    公开(公告)日：1996-08-01

    申请号：DE68926740

    申请日：1989-04-25

    Applicant: IBM

    Inventor： BADAOUI MOHAMED ,  CALVIGNAC JEAN ,  CARLE GUY ,  GARCIA CHRISTIAN ,  VACHEE PIERRE

    IPC: H04L29/10 ,  G06F13/38 ,  H04L12/28

    Abstract: Interconnection system for attaching a maximum number n of equipment users EU (DCE or DTE) to the line adapter 2 of a communication processing unit. The user data and control bits are carried on transmit and receive serial link 4 and 6 in data and control slot entities arranged in frame of period T, comprising one entity per user. These entities are allocated to the user equipments through multiplexing/demultiplexing circuit 10, link adapters 12-1 to 12-8 and connecting boxes 30-1 to 30-8. The user equipments are connected though active remote modules which are specific to the standardized interfaces of the user equipments. Link adapters 12-1 to 12-8 add to the data and control slot entities an outband slot which is used for exchanging control information, such as the active remote module address and type which are stored in memory 42, to be transmitted to the line adapter 2. The advantage of the interconnection system is that the attachment of the user equipments is simplified.

    57.
    发明专利
    未知

    公开(公告)号：DE69022025T2

    公开(公告)日：1996-04-18

    申请号：DE69022025

    申请日：1990-03-13

    Applicant: IBM

    Inventor： BARUCCHI GERARD ,  GALCERA JOSE ,  TOUBOL GILLES ,  CALVIGNAC JEAN ,  ORSATTI DANIEL ,  TRACOL ANDRE

    IPC: G06F1/12 ,  H03L7/06 ,  H04J3/06 ,  H04L7/00

    Abstract: The synchronization circuit resynchronizes the data bits received from remote devices from line or link 20-1 with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in a n-bit cyclic buffer (114-1) with the received bit clock CS and they are sequentially picked at the opposite buffer position with the central clock CO The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.

    58.
    发明专利
    未知

    公开(公告)号：DE68916413T2

    公开(公告)日：1995-01-26

    申请号：DE68916413

    申请日：1989-03-14

    Applicant: IBM

    Inventor： BARUCCHI GERARD ,  CALVIGNAC JEAN ,  ORSATTI DANIEL ,  TRACOL ANDRE

    IPC: G06F15/16 ,  G06F15/167 ,  G06F15/173

    Abstract: The system performs an optimized number of simultaneous transfers of data packets between pairs of units comprising an origin unit and a target unit selected among N data processing units (8). Each data processing unit comprises a set of outbound queues with one outbound queue associated with each one of the data processing units to which it may send data packets, for storing the data packets to be sent by the data processing unit to the data processing unit associated with said one outbound queue. The transfers are performed during a time burst Ti+1 by data switch 6 under control of switching control signals sent to data switch by the units on lines 16-1 to 16-N in response to control out signals generated by scheduler 4 during previous burst time Ti. The scheduler runs a selection algorithm which gives each unit an equal probability to be selected as origin unit in a given period.

    59.
    发明专利
    未知

    公开(公告)号：DE3785211T2

    公开(公告)日：1993-10-07

    申请号：DE3785211

    申请日：1987-10-30

    Applicant: IBM

    Inventor： CALVIGNAC JEAN ,  DAUPHIN MICHEL ,  LENOIR RAYMOND ,  PICARD JEAN-LOUIS

    IPC: H03M13/00 ,  H03M13/09 ,  H04L1/00

    Abstract: A process for updating the frame check sequence FCSr(x) of a digital frame including an embedded variable header polynomial Hr(x), said process including : XORing the modified polynomial header Ht(x) and previous polynomial header Hr(x) to generate a differential polynomial D(x); computing a differential frame check polynomial sequence dFCS (x) on said D(x) and adding dFCS(x) to the polynomial FCSr(x).

    60.
    发明专利
    未知

    公开(公告)号：DE3883528D1

    公开(公告)日：1993-09-30

    申请号：DE3883528

    申请日：1988-06-16

    Applicant: IBM

    Inventor： CALVIGNAC JEAN ,  FERAUD JACQUES ,  NAUDIN BERNARD ,  PIN CLAUDE LES JARDINS DE CESS ,  SAINT-GEORGES ERIC

    IPC: H04L29/02 ,  H04L29/06 ,  H04L29/08 ,  H04L12/00

    Abstract: This invention relates to a parallel processing method and device for receiving and transmitting HDLC (high level data link control) frames, which improves the performance of a data communication apparatus in a significant way. The bit streams transporting the frames, received from lines 6 are inputted in to register 12, in such a way that n bits are processed during a time interval T. Parallel processor 10 counts the consecutive bits at 1 from the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result it rassembles N-bits characters, with N>n, in register 16. The frame characters to be sent on lines 6 are stored into register 28, and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive 1 as a function of the value of the N-bits and as a function of the bit of the previous character, to store into register 32, the bits which are sent on lines 6.

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