公开(公告)号：DE112021000187T5

公开(公告)日：2022-09-29

申请号：DE112021000187

申请日：2021-01-05

Applicant: IBM

Inventor： REZNICEK ALEXANDER ,  GLUSCHENKOV OLEG ,  SULEHRIA YASIR ,  SIL DEVIKA

IPC: H01L27/22 ,  H01L21/428 ,  H01L21/768 ,  H01L23/52 ,  H01L43/08

Abstract: Bitleitungen aus einem grobkörnigen Metall werden über Säulen mit einem magnetischen Tunnelübergang gebildet, die als MRAM-Bits verwendet werden, ohne die magnetischen Eigenschaften der magnetischen Tunnelübergänge maßgeblich zu beeinflussen. Eine Bitleitung aus Kupfer oder einer Kupfer-Legierung mit vergleichsweise kleinen Körnern wird über den Säulen gebildet. Ein Tempern mit einem Laser wird eingesetzt, um die Bitleitung zu schmelzen. Eine nachfolgende Abkühlung und Rekristallisation resultiert in einer Reduktion der Anzahl von Korngrenzen in der Bitleitung und einer Reduktion des effektiven spezifischen elektrischen Widerstands der Bitleitung. Es können mehrere Schmelz-/Abkühl-Zyklen verwendet werden. In einer resultierenden Struktur sind Körner der Bitleitung zu den Säulen vertikal ausgerichtet.

公开(公告)号：AU2021212356A1

公开(公告)日：2022-06-16

申请号：AU2021212356

申请日：2021-01-05

Applicant: IBM

Inventor： REZNICEK ALEXANDER ,  GLUSCHENKOV OLEG ,  SULEHRIA YASIR ,  SIL DEVIKA

IPC: H01L43/08

Abstract: Large grain metal bitlines are formed above magnetic tunnel junction pillars used as MRAM bits without materially affecting the magnetic properties of the magnetic tunnel junctions. A copper or copper alloy bitline having relatively small grains is formed over the pillars. Laser annealing is employed to melt the bitline. Subsequent cooling and recrystallization results in a reduction of the number of grain boundaries in the bitline and a reduction in bitline effective resistivity. Multiple melt/cool cycles may be used. Bitline grains are vertically aligned with the pillars in a resulting structure.

公开(公告)号：DE112015003641T5

公开(公告)日：2017-05-18

申请号：DE112015003641

申请日：2015-09-01

Applicant: IBM

Inventor： DESHPANDE VEERESH VIDYADHAR ,  DESHPANDE SADANAND VINAYAK ,  CORLISS DANIEL ,  GLUSCHENKOV OLEG ,  KRISHNAN SIVARAMA

IPC: H05G2/00

Abstract: Ein Pellet als Strahlungsquelle für extremes Ultraviolett (EUV) enthält mindestens ein Metallpartikel, das von einem schweren Edelgascluster umschlossen ist, das wiederum innerhalb eines Edelgashüllenclusters enthalten ist. Das EUV-Strahlungsquellengebilde kann durch aufeinander folgende Bestrahlung mit mindestens einem ersten Laserimpuls und mit mindestens einem zweiten Laserimpuls aktiviert werden. Durch jeden ersten Laserimpuls wird ein Plasma erzeugt, indem Elektronen der äußeren Orbitale von dem mindestens einen Metallpartikel abgetrennt und in den schweren Edelgascluster freigesetzt werden. Durch jeden zweiten Laserimpuls wird das von dem schweren Edelgascluster umschlossene Plasma verstärkt und ein laserinduzierter Selbstverstärkungsprozess ausgelöst. Durch das verstärkte Plasma werden Übergänge zwischen Orbitalen von Elektronen des schweren Edelgases und anderen enthaltenen Atomen ausgelöst, wodurch es zur Emission von EUV-Strahlung kommt. Die Laserimpulseinheiten können mit einer Einheit zum Erzeugen von Strahlungsquellenpellets kombiniert werden, um ein komplettes EUV-Strahlungsquellensystem zu bilden.

公开(公告)号：DE602005024611D1

公开(公告)日：2010-12-16

申请号：DE602005024611

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

公开(公告)号：DE10246306B4

公开(公告)日：2009-05-07

申请号：DE10246306

申请日：2002-10-04

Applicant: IBM ,  QIMONDA AG

Inventor： CHUDZIK MICHAEL ,  GLUSCHENKOV OLEG ,  JAMMY RAJARAO ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/8242 ,  H01G4/06 ,  H01L21/316 ,  H01L21/321

Abstract: An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

公开(公告)号：AT427563T

公开(公告)日：2009-04-15

申请号：AT06777968

申请日：2006-07-25

Applicant: IBM

Inventor： DORIS BRUCE ,  COSTRINI GREGORY ,  GLUSCHENKOV OLEG ,  LEONG MEIKEI ,  SEONG NAKGEUON

IPC: H01L27/11 ,  H01L21/8244

Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

公开(公告)号：DE10244569B4

公开(公告)日：2006-08-10

申请号：DE10244569

申请日：2002-09-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT ,  WEYBRIGHT MARY

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/51

Abstract: Disclosed is a method of processing a semiconductor gate structure on a semiconductor wafer, the method comprising providing a semiconductor structure with an active device area capped with a pad oxide layer bounded by one or more isolation trenches, providing a sacrificial oxide layer by thickening said pad oxide layer to a desired oxide thickness, in using said thickened pad oxide layer as said sacrificial oxide layer for device implantation, stripping said sacrificial pad oxide layer after use, and capping said semiconductor gate with a final gate oxide layer.

公开(公告)号：DE102004004594A1

公开(公告)日：2004-09-09

申请号：DE102004004594

申请日：2004-01-29

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MALIK RAJEEV ,  RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  GLUSCHENKOV OLEG ,  YAN HONGWEN ,  YANG HAINING

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal layers comprising a gate metalis provided. The gate metal is recessed away from the gate stack sidewall using a chemical etch. The gate metal of the gate stack structure is selectively oxidized to form a metal oxide that at least partly fills the recess.

公开(公告)号：DE10305729A1

公开(公告)日：2003-08-28

申请号：DE10305729

申请日：2003-02-12

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHAKRAVARTI ASHIMA B ,  GLUSCHENKOV OLEG ,  MCSTAY IRENE

IPC: C23C16/04 ,  C23C16/44 ,  C23C16/455 ,  C23C16/48 ,  C23C16/52 ,  H01L21/00 ,  H01L21/316 ,  H01L21/318 ,  H01L21/8242 ,  H01L21/3205 ,  H01L21/324

Abstract: An apparatus (110) and method for depositing material on a semiconductor wafer with non-planar structures (114). The wafer (114) is positioned in a chamber (111), and reactive gases (132) are introduced into the chamber (111). The gases (132) and wafer (114) are heated, wherein the gas (132) temperature in the process chamber (111) and in the vicinity of the wafer (114) surface is lower than the temperature of the wafer (114) surface. A material is deposited on the wafer (114) surface using chemical vapor deposition. A gas cooler may be utilized to lower the temperature of the reactive gases (132) while the wafer (114) is heated.

公开(公告)号：AU2002239671A1

公开(公告)日：2002-11-11

申请号：AU2002239671

申请日：2001-12-27

Applicant: IBM

Inventor： KAPLAN RICHARD ,  DOKUMACI OMER ,  KHARE MUKESH ,  GLUSCHENKOV OLEG ,  HEDGE SURYANARAYAN G

IPC: H01L29/786 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/31

Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, Cl, He, Ar, Kr, and Xe; and mixtures thereof.