公开(公告)号：DE10026243C2

公开(公告)日：2002-04-18

申请号：DE10026243

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT

IPC: G11C17/00 ,  G11C17/18 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/66 ,  H01L23/525 ,  G11C29/00

Abstract: The fuse state read-out method uses application of a voltage (Vblh) to the fuse which has a reduced voltage level relative to an internal voltage (Vint) of the semiconductor memory device, e.g. a voltage level which is reduced by between 20 and 30 % relative to an internal voltage of about 2 V, for defining the high potential of the bit lines (BL) of the memory cell field (6).

公开(公告)号：DE10034255A1

公开(公告)日：2002-01-31

申请号：DE10034255

申请日：2000-07-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JOHNSON BRET ,  PLAETTNER ECKHARD ,  SCHNEIDER HELMUT

IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/407

Abstract: A circuit arrangement for reading and writing binary information to a storage location array having a matrix-type arrangement of rows and columns, has a switching device (T9) which interrupts the current supply, after excitation of a any word-line, to the latch-flip-flops (T1-T4) in the write-read circuits (LV2) under control of a column-selection signal (SAS), at a time-point not before the relevant latch-flip-flop has assumed a condition indicating the information content of the accessed memory location, and which at the latest occurs in the active interval of the relevant column-selection signal.

公开(公告)号：DE59801722D1

公开(公告)日：2001-11-15

申请号：DE59801722

申请日：1998-11-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAVIGNAC DOMINIQUE ,  FEURLE ROBERT ,  SCHNEIDER HELMUT

IPC: G11C11/405 ,  G11C5/14 ,  G11C11/4074 ,  H02J9/06

Abstract: An integrated memory includes two potential nodes at which a supply voltage is present. Memory cells each have a selection transistor and a storage capacitor. At least one series circuit is disposed between the two potential nodes. The series circuits each have at least one buffer capacitor and one associated transistor. The associated transistor effects current limiting in the event of a defect in the at least one buffer capacitor. Each of the buffer capacitor and associated transistor have a mutual configuration and dimensions like the selection transistor and storage capacitor of one of the memory cells and have only an electrical connection differing from the selection transistor and storage capacitor.

公开(公告)号：DE19946203A1

公开(公告)日：2001-04-19

申请号：DE19946203

申请日：1999-09-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER HELMUT ,  FEURLE ROBERT

IPC: H01L23/525 ,  H01L27/112

Abstract: The support structure has a metal track (7) on a lower metallization plane connected with a fuse (12) on a top metallization plane via a contact hole (11). The track is provided on an insulator layer (3) which comprises an embedded gate conductor (4,5,6). The gate conductor (5,9) is provided within the insulator layer below the metal track to be supported. The gate conductor (4,5,6;9) preferably comprises doped polycrystalline silicon.

公开(公告)号：DE50014661D1

公开(公告)日：2007-10-31

申请号：DE50014661

申请日：2000-03-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER HELMUT ,  LINDOLF JUERGEN DR ,  BORST THOMAS ,  RUCKERBAUER HERMANN

IPC: H01L21/761 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H03F3/16

Abstract: The field effect transistor (10) is located in a trough (9) formed by an n+ type conduction buried layer (5) and n-type conduction diffusion regions (7,8). The gate to source voltage (Vth) can be controlled by adjusting the negative trough potential (VBS)

公开(公告)号：DE50111772D1

公开(公告)日：2007-02-15

申请号：DE50111772

申请日：2001-05-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRASS ECKHARD DR ,  SCHAFFROTH THILO ,  SCHNABEL JOACHIM ,  SCHNEIDER HELMUT

IPC: G01R31/28 ,  G11C29/00 ,  G11C11/401 ,  G11C29/12 ,  G11C29/26 ,  H01L27/10

Abstract: A method for testing a multiplicity of word lines of a semiconductor memory configuration in a multiple word line wafer test is described. To prevent a pulling-up of inactive word lines which are at a negative voltage when the active word lines are ramped down, the inactive word lines are decoupled from the negative word line voltage and are connected to a high impedance shortly before the active word lines are ramped down.

公开(公告)号：DE102005036288A1

公开(公告)日：2007-02-08

申请号：DE102005036288

申请日：2005-08-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNABEL FLORIAN ,  SCHNEIDER HELMUT

IPC: G01R31/28

Abstract: The probe (31) has a probe tip (32) for contacting a circuit to be tested, and a repeater (34) for isolating the probe tip from a set of signal lines (S 1, S 2, S i). A potential adjacent to the probe tip is transmitted to the signal lines, and a switching device (35) conductively connects the probe tip with one of the signal lines in such a manner that excitation signal applied to one of the signal lines is injectable into the circuit to be tested. An independent claim is also included for a method for operating an active probe.

公开(公告)号：DE102005030372A1

公开(公告)日：2007-01-04

申请号：DE102005030372

申请日：2005-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EGERER JENS ,  SCHNEIDER HELMUT ,  BARTENSCHLAGER RAINER

IPC: G11C11/4074 ,  G11C7/06 ,  G11C11/4063

Abstract: A method and a device for regulating the threshold voltage of a transistor is disclosed. The device includes a circuit configured for modifying a voltage applied at a bulk connection of the transistor such that the threshold voltage of the transistor is substantially temperature-independent at least in a first temperature range. In one embodiment, the device includes a memory device, and the transistor is a transistor of a sense amplifier of the memory device.

公开(公告)号：DE10026276B4

公开(公告)日：2006-02-16

申请号：DE10026276

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT ,  SCHAMBERGER FLORIAN ,  SCHAFFROTH THILO

IPC: G11C16/02 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

Abstract: The explicit high voltage source (1) and internal low voltage source (2) are selectively connected to respective connection areas (4,5) of a programmable fuse (3) by respective connectors (6,7). The switches (8,9) connect the connectors to the connection areas, when a control signal is applied to the switches from a controller (16), to apply required voltage.

公开(公告)号：DE102004010191A1

公开(公告)日：2005-09-29

申请号：DE102004010191

申请日：2004-03-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL BERNHARD ,  SCHNEIDER HELMUT

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091