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    Higher voltage switch for level-translation for use in memory circuits, has first circuit branch with transistor and resistance, and second parallel branch with two transistors.
    51.
    发明专利
    Higher voltage switch for level-translation for use in memory circuits, has first circuit branch with transistor and resistance, and second parallel branch with two transistors. 未知

    公开(公告)号：FR2803456A1

    公开(公告)日：2001-07-06

    申请号：FR9916818

    申请日：1999-12-31

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VARISCO LAURA

    IPC: H01L27/088 ,  H01L29/423 ,  H03K19/003 ,  H03K19/0944 ,  H03K17/56 ,  G11C16/12

    Abstract: The high voltage switch has first circuit branch with high voltage field effect transistor and a resistance. There is a second parallel branch with two field effect transistors connected in series. The lower of these is a high voltage type, and the switch output is taken from the connection between these two transistors. The higher voltage switch comprises a first branch with a resistor (R) and a first MOS transistor of n-type (HT1) connected in series, and a second branch with two MOS transistors of n-type (HT2,HT3) connected in series, where both branches are connected between the higher voltage node (N1) and the ground. The connection point (B) between the second and third transistors gives the output signal (Out), and the second transistor (HT2) is controlled by the gate connected to the connection point (A) between the resistor (R), e.g. 20 kOhm, and the first transistor (HT1). The transistors are higher voltage MOS transistors of drift type with the drain formed by a structure with a well region and field oxide, or floating-gate type which is used as the control gate and comprises an oxide tunnel and gradual junction.

    Device for reading integrated circuit memory
    52.
    发明专利
    Device for reading integrated circuit memory 未知

    公开(公告)号：FR2801719A1

    公开(公告)日：2001-06-01

    申请号：FR9915114

    申请日：1999-11-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  VARISCO LAURA

    IPC: G11C7/08 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28

    Abstract: The reading device comprises a differential amplifier (2) with inputs (MTX, REF) each connected to the output (SR, SD) of respective current-voltage converter (CIVD, CIVR), whose inputs are connected to the selected bit and reference bit lines (Bl, Blref), respectively, where each converter can precharge the associated bit line to a first precharge voltage (Vbias 1) in the precharge phase, a read current generator (GEN) for establishing the data at device output in the following estimation phase, circuits (PCHMTX, PCHREF) for precharging the inputs of differential amplifier to a second precharge voltage (Vbias 2), which is between the first precharge voltage (Vbias 1) and the supply voltage (Vdd), and a circuit (50) in the control block for detecting the end of precharge phase in order to stop the precharge and activate the read current generator (GEN) for the estimation phase. The read current generator (GEN) receives a control signal (MIR) for deactivation in the precharge phase and activation in the estimation phase, where the signal is provided by a control block (5) comprising the circuit (50) for detecting the voltage drop at the input (ER) of converter, and a logic circuit (51). The second precharge voltage (Vbias 2) is about 1.5 V. The device in detailed embodiment also comprises means for equalization of internal nodes controlled by the signal (MIR), and the means are in the form of passgates. Each converter (CIVD, CIVR) comprises a transistor (T1) connected between input and output of converter, and an inverter (I1) connected between the input of converter and the gate of transistor. The circuit (50) comprises two inverters, one dimensioned so to detect the voltage drop before the other associated with the reference bit line. An integrated circuit memory comprises a reading device according to the invention.

    55.
    发明专利
    未知

    公开(公告)号：DE69418976D1

    公开(公告)日：1999-07-15

    申请号：DE69418976

    申请日：1994-11-08

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  FRUHAUF SERGE ,  TAILLET FRANCOIS

    IPC: B42D15/10 ,  G06K19/07 ,  G06K19/077 ,  H01L21/82 ,  H01L27/02

    Abstract: The invention relates to fuses for an integrated circuit. Such fuses are useful for irreversibly preventing access to certain regions of the integrated circuit. They serve particularly in applications for memory cards. According to the invention, a fuse is provided consisting of an NP junction of shallow depth (12, 11) covered by a metal contact (22), the semiconducting region covered over not being heavily doped. In order to blow the fuse, the junction is forward-biased with a current which is sufficient to allow diffusion of metal as far as the junction, which short-circuits it. Detection is carried out also by forward-biasing the junction, but with a low current or a low voltage. Detection can also be carried out in reverse bias.

    PROCEDE DE FABRICATION D'UN DISPOSITIF A EMPILEMENT DE PUCES SEMICONDUCTRICES
    57.
    发明专利
    PROCEDE DE FABRICATION D'UN DISPOSITIF A EMPILEMENT DE PUCES SEMICONDUCTRICES 未知

    公开(公告)号：FR2967815A1

    公开(公告)日：2012-05-25

    申请号：FR1059594

    申请日：2010-11-22

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  DAUTRICHE PIERRE

    IPC: H01L23/538

    Abstract: L'invention concerne un procédé de fabrication d'un dispositif à empilement de puces semiconductrices, comportant les étapes suivantes : a) former une première matrice de connecteurs (11) sur une face d'une première puce semiconductrice (C1) ; b) former une seconde matrice de connecteurs (12) sur une face d'une seconde puce semiconductrice (C2), la seconde matrice comprenant plus de connecteurs que la première matrice et le pas de la première matrice étant un multiple du pas de la seconde matrice ; c) appliquer la première puce contre la seconde puce ; et d) établir des signaux de test entre les première (C1) et seconde (C2) puces pour déterminer l appariement entre les connecteurs (11) de la première matrice et les connecteurs (12) de la seconde matrice.

    PROCEDE DE LITHOGRAPHIE D'UNE PLAQUETTE SEMICONDUCTRICE
    58.
    发明专利
    PROCEDE DE LITHOGRAPHIE D'UNE PLAQUETTE SEMICONDUCTRICE 未知

    公开(公告)号：FR2966974A1

    公开(公告)日：2012-05-04

    申请号：FR1058894

    申请日：2010-10-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD

    IPC: H01L21/027 ,  G03F7/20 ,  H01J37/317 ,  H01L21/08 ,  H01L21/268

    Abstract: L'invention concerne un procédé de lithographie 1 d'une plaquette semiconductrice comprenant : - une étape 2 de dépôt d'une résine photosensible sur la surface supérieure de la plaquette semiconductrice, - une étape 3 d'exposition de la résine à un rayonnement électromagnétique pour définir des premières régions exposées, et - une étape 4 d'exposition de la résine à un faisceau d'électrons pour définir des deuxièmes régions exposées.

    59.
    发明专利
    未知

    公开(公告)号：DE60330130D1

    公开(公告)日：2009-12-31

    申请号：DE60330130

    申请日：2003-01-31

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  DRAY CYRILLE ,  FOURNEL RICHARD ,  POIRIER SEBASTIEN ,  CASPAR DANIEL ,  CANDELIER PHILIPPE

    IPC: H01L29/788 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

    Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

    60.
    发明专利
    未知

    公开(公告)号：AT449424T

    公开(公告)日：2009-12-15

    申请号：AT03709915

    申请日：2003-01-31

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  DRAY CYRILLE ,  FOURNEL RICHARD ,  POIRIER SEBASTIEN ,  CASPAR DANIEL ,  CANDELIER PHILIPPE

    IPC: H01L29/788 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

    Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

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