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公开(公告)号：DE69411532D1
公开(公告)日：1998-08-13
申请号：DE69411532
申请日：1994-02-17
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA MARIA , MACCARRONE MARCO
Abstract: A method for programming non-volatile row redundancy memory registers (RR1-RR4) each one associated to a respective pair of redundancy row and each one programmable to store in two subsets (1,2;1,2') of a set of memory cells (MC0-MC9) a pair of addresses of a respective pair of adjacent defective rows; each memory register is supplied with row address signals (R0-R9) and with a respective selection signal (C0-C3) belonging to a set of column address signals (CABUS); the method provides for: applying to the row address signals (R0-R9) the address of a first defective row of the pair of adjacent defective rows; activating one of the selection signals (C0-C3) for selecting the memory register which is to be programmed; applying to a further column address signal (C4) a first logic level to select for programming, in the selected memory register, a first subset (1,2) of memory cells (MC0-MC9); enabling the programming of the address of the first defective row of the pair of adjacent defective rows into the first subset (1,2) of memory cells; applying to at least a subset (R0-R3) of the row address signals (R0-R9) the address of the second defective row of the pair; applying to the further column address signal (C4) a second, opposite logic level to select for programming, in the selected memory register (RR1-RR4), at least a group (2') of memory cells (MC0-MC3) of the second subset (1,2') of the two subsets (1,2;1,2') of memory cells; enabling the programming of the address of the second defective row of the pair of adjacent defective rows into the second subset (1,2') of memory cells.
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公开(公告)号：DE69629669T2
公开(公告)日：2004-07-08
申请号：DE69629669
申请日：1996-06-18
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , MICHELONI RINO , MACCARRONE MARCO
Abstract: The read circuit presents a current mirror circuit (9) including a first and second load transistor (12, 13) interposed between the supply line (15) and a respective first and second output node (16, 17); the first output node (16) is connected to a cell (4) to be read; the second output node (17) is connected to a generating stage (20, 51) generating a reference current (IR1) having a predetermined characteristic; and the size of the second load transistor (13) is N times greater than the first load transistor (12). To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit (55) presents a current balancing branch (75) connected between the first output node (16) and ground for generating an equalizing current (IB) presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.
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公开(公告)号：DE69728148D1
公开(公告)日：2004-04-22
申请号：DE69728148
申请日：1997-11-05
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , MICHELONI RINO , MACCARRONE MARCO , ZAMMATTIO MATTEO
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公开(公告)号：DE69631583D1
公开(公告)日：2004-03-25
申请号：DE69631583
申请日：1996-04-30
Applicant: ST MICROELECTRONICS SRL
Inventor： MACCARRONE MARCO , GHEZZI STEFANO , BRANCHETTI MAURIZIO
Abstract: The present invention concerns a redundant UPROM cell (1) incorporating at least one memory element (P0) of the EPROM or flash type having a control terminal (CG) and a conduction terminal (X) to be biased, a register (2) with inverters connected to the memory element and MOS transistors (M1,M3) connecting said memory element (P0) with a reference low voltage power supply (Vdd). There is provided a precharge network (5) for the conduction terminal (X) of the flash cell and said network (5) incorporates a complementary pair of transistors (M4,M5). The second transistor (M5) of said pair (M4,M5) is a natural N-channel MOS type. With the UPROM cell (1) is associated a circuit portion (10) for generating at output (U) a live signal (UPCH) to be applied to the control terminal of the second transistor (M5) with the portion (10) comprising a timing section (7) and a generation section (8) for said second live signal (UPCH).
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公开(公告)号：DE69631518D1
公开(公告)日：2004-03-18
申请号：DE69631518
申请日：1996-04-30
Applicant: ST MICROELECTRONICS SRL
Inventor： MACCARRONE MARCO , MULATTI JACOPO , GOLLA CARLA MARIA
Abstract: A circuit (1) for generating biasing signals in reading of a redundant UPROM cell (2) incorporating at least one memory element (FC) of the EPROM or flash type and having a control terminal (GC) and a conduction terminal (DC) to be biased as well as MOS transistors (M1,M2) connecting said memory element (FC) with a reference low supply voltage (Vcc) comprises a voltage booster (3) for generating at output (U1) a first voltage signal (UGV) to be applied to the control terminal (GC) of the memory element (FC) and a limitation network (5) for said voltage signal (UGV) connected to the output (U1) of the voltage booster (3). There is also provided a circuit portion (10) for generating at output (U2) a second voltage signal (Vb) to be applied to the control terminal of one (M2) of the above mentioned transistors (M1,M2). This circuit portion (10) comprises a timing section (7) interlocked with the voltage booster (3) of a section (8) generating the second voltage signal (Vb).
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Patent Agency Ranking
公开(公告)号：DE69629669D1
公开(公告)日：2003-10-02
申请号：DE69629669
申请日：1996-06-18
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , MICHELONI RINO , MACCARRONE MARCO
Abstract: The read circuit presents a current mirror circuit (9) including a first and second load transistor (12, 13) interposed between the supply line (15) and a respective first and second output node (16, 17); the first output node (16) is connected to a cell (4) to be read; the second output node (17) is connected to a generating stage (20, 51) generating a reference current (IR1) having a predetermined characteristic; and the size of the second load transistor (13) is N times greater than the first load transistor (12). To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit (55) presents a current balancing branch (75) connected between the first output node (16) and ground for generating an equalizing current (IB) presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.
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公开(公告)号：IT1313226B1
公开(公告)日：2002-06-17
申请号：ITMI991475
申请日：1999-07-02
Applicant: ST MICROELECTRONICS SRL
Inventor： MULATTI JACOPO , MACCARRONE MARCO
Abstract: Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted references are in turn connected to first, second and third adjusters, which are adapted to provide respective first, second and third voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture. At least a first switch block is used that connects between the first and third circuit nodes and is controlled by a first control signal to place the first and third high-voltage references in parallel during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively speed up the charging of the first circuit node so as to shorten the settling time of the first voltage reference. A method is also presented for generating voltage references with a reduced value of settling time as produced within a memory architecture.
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公开(公告)号：DE69427277T2
公开(公告)日：2001-09-13
申请号：DE69427277
申请日：1994-01-31
Applicant: ST MICROELECTRONICS SRL
Inventor： OLIVO MARCO , MACCARRONE MARCO
Abstract: A new method for testing an electrically programmable non-volatile memory and comprising a cell matrix and a state machine which governs the succession and timing of the memory programming phases by means of some control signals (WEN, CEN, OEN and DU) provides exclusion of the internal state machine and modification of the meaning of at least one of the control signals (WEN, CEN, OEN and DU) to program directly the cell matrix and then verify programming correctness.
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公开(公告)号：DE69427277D1
公开(公告)日：2001-06-28
申请号：DE69427277
申请日：1994-01-31
Applicant: ST MICROELECTRONICS SRL
Inventor： OLIVO MARCO , MACCARRONE MARCO
Abstract: A new method for testing an electrically programmable non-volatile memory and comprising a cell matrix and a state machine which governs the succession and timing of the memory programming phases by means of some control signals (WEN, CEN, OEN and DU) provides exclusion of the internal state machine and modification of the meaning of at least one of the control signals (WEN, CEN, OEN and DU) to program directly the cell matrix and then verify programming correctness.
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公开(公告)号：DE69421266T2
公开(公告)日：2000-05-18
申请号：DE69421266
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
Abstract: The circuit (1) comprises a section (2) generating a pulse signal (ATD) for asynchronously enabling the read phases; a section (4) generating precharge (PC) and detecting (DET) signals of adjustable duration, for controlling data reading from the memory (104) and data supply to the output buffers (106); a section (5) generating a noise suppressing signal (N) for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal (SP) in an out-like circuit (33); a section (6) generating a loading signal (L), the duration of which may be equal to that of the noise suppressing signal (N) or extended by an extension circuit (51) in the event the array presents slower elements which may thus be read; and a section (7) generating a circuit reset signal (END).
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