公开(公告)号：JP2001036058A

公开(公告)日：2001-02-09

申请号：JP19767799

申请日：1999-07-12

Applicant: UNITED MICROELECTRONICS CORP

Inventor： HAN ZUISHO ,  RI JIKA

IPC: H01L31/10 ,  H01L27/146

Abstract: PROBLEM TO BE SOLVED: To obtain a manufacture for a MOS sensor having improved sensitivity. SOLUTION: A P-type region 104 extending into a substrate 100 is formed. A laminated polysilicon structure 115 is formed on the P-type region 104. Next, the laminated polysilicon structure 115 is used as an implantation buffer layer, and ions are implanted into the P-type region to form an N-type region 120 extended to the substrate at a shallow depth. The laminated polysilicon structure 115 is patterned and etched to form a laminated polysilicon ring 122, exposing partially the N-type region 120 on the P-type region. A metal wiring 130 for electrically connecting the laminated polysilicon ring structure with a MOS transistor gate is formed.

公开(公告)号：JP2000330258A

公开(公告)日：2000-11-30

申请号：JP13983099

申请日：1999-05-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN KINRYU

IPC: H01L21/027 ,  G03F1/36 ,  G03F1/68 ,  G03F1/08

Abstract: PROBLEM TO BE SOLVED: To obtain a method for correcting optical proximity. SOLUTION: Main patterns 300 having critical dimensions are supplied. When the critical dimensions are a first reference value or below the value, serifs 304 (projecting patterns for correction)/hammer heads (hammer-like patterns for correction) are added to the main patterns 300. When the critical dimensions are a second reference value smaller than the first reference value or below the value, auxiliary patterns 302 are added to the main patterns 300. The corrected patterns are transferred onto the layer on a wafer with high fidelity.

公开(公告)号：JP2000306862A

公开(公告)日：2000-11-02

申请号：JP11084699

申请日：1999-04-19

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SHA CHOKEI ,  O KONCHI ,  SHA BUNEKI

IPC: H01L21/768 ,  C23C14/50 ,  H01L21/203 ,  H01L21/285

Abstract: PROBLEM TO BE SOLVED: To provide a method for uniformly coating the sidewall of a contact hole of a silicon wafer in a stepwise manner. SOLUTION: In coating the side of wall of a contact hole by a PVD method, a rotary pedestal 32 capable of tilting at a certain angle is used, a silicon wafer 30 having a plurality of contact holes therein is placed on the pedestal in a reaction chamber, a metal layer is deposited on the bottom surfaces of the contact holes with the pedestal disposed perpendicular to the depositing direction, the position of the pedestal is adjusted so that a normal of the pedestal forms a tilt angle with respect to the depositing direction, and finally the pedestal 32 is rotated to attain uniform deposition onto inner sidewalls of the contact holes of the silicon wafer.

公开(公告)号：JP2000243829A

公开(公告)日：2000-09-08

申请号：JP13182298

申请日：1998-05-14

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RI CHIJIN

IPC: H01L21/302 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To lessen misalignment which occurs in a process where a via and a trench are formed by a method wherein a dual damask structure is formed using a layer of polysilicon or silicon nitride as a mask. SOLUTION: Two stop layers 306 and 310 are formed through two injection processes. An anisotropic etching operation is carried out using these stop layers. By this setup, a via and a trench are formed. The via and the trench are filled up with a conductive layer 314, and then the conductive layer 314 located above the stop layer 310 is removed, by which a dual damask structure is finished. An etching stop function can be easily controlled. A spacer can be used instead of a large number of masks. By this setup, misalignment can be protected.

公开(公告)号：JP2000235981A

公开(公告)日：2000-08-29

申请号：JP3925599

申请日：1999-02-17

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO SHOGEN ,  GO SHUNGEN ,  RO KATETSU

IPC: H01L21/3205 ,  H01L21/304

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a waveform pattern for the formation of a contact or a conductive wire. SOLUTION: A substrate 200 having an opening part for forming a double waveform pattern, a waveform pattern or a mutual connection is used. A barrier layer 206 having the same shape as that of the substrate 200 is formed thereon, and then a seed layer is formed on the opening part. A metal layer 210 is selectively formed for filling the opening part. A mechanochemical polishing step is performed until the substrate 200 is exposed.

公开(公告)号：JP2000216374A

公开(公告)日：2000-08-04

申请号：JP961699

申请日：1999-01-18

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN SHINRAI ,  YO BUNKAN ,  SHU SHIBUN

IPC: H01L29/78 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a MOS transistor. SOLUTION: In this manufacture, a gate oxide layer 202, a polysilicon layer 204, a barrier layer 206, and a conductor layer 208 are made continuously on a substrate. A part of the conductor layer and a part of the barrier layer are removed until the polysilicon layer is exposed, by executing a photolithographic/ etching process. Next, ion implantation is conducted, using a remaining conductor layer 208a and a remaining barrier layer 206a as a mask, so as to form a lightly-doped region 212. A spacer 214 is made on the sidewall of the conductor layer and on the sidewall of the barrier layer. The remaining conductor layer, the polysilicon layer in a position other than the spacer, and the gate oxide layer are removed. The remaining conductor layer and the remaining polysilicon layer constitute a gate having a cross section in the shape of inverted T. A source/drain region which includes a low-doped region is made within the substrate by the ion implantation, using a gate structure as a mask.

公开(公告)号：JP2000208437A

公开(公告)日：2000-07-28

申请号：JP301499

申请日：1999-01-08

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN KENTEI ,  SHU SHIBUN

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a self-alignment silicide (salicide) layer. SOLUTION: A method for forming a silicide layer includes a pre-amorphous implanting step before a salicide process. In the pre-amorphous implanting step, impact is applied to a silicon surface of the substrate 200 using BF2+ ions, and an amorphous layer 22 is formed thereon. The salicide step includes a step for forming a metallic layer 210 on the substrate 200, a step for forming a salicide layer 212 on a silicon surface in a rapid thermal process(RTP), and a step for removing a metallic layer 210 that is not reactivated.

公开(公告)号：JP2000021886A

公开(公告)日：2000-01-21

申请号：JP30432898

申请日：1998-10-26

Applicant: UNITED MICROELECTRONICS CORP

Inventor： LIOU FU-TAI

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To simply make local interconnections by forming a heat-resistive metal oxide layer on a substrate, treating any part thereof with H to convert to a semiconductor or conductor acting as local interconnections. SOLUTION: A semiconductor substrate 100 has e.g. an MOS device 101 and electrolytic oxide layer 102 (if having a plurality of devices, the devices are insulated), e.g. heat-resistive metal oxide layer 103 composed of a TiO2 layer, Ta2O5 layer, Fe2O3 layer, BaTiO3 layer or combined layer thereof is formed on the entire surface of the substrate 100 and partly covered with a mask layer 104, and the H plasma or H heat treatment is applied to the part 103b covered with the mask layer 104 and exposed part 103a with the mask layer 104 used as a mask or diffusion barrier layer. This improves the conductivity of the exposed part 103a of the heat-resistive metal oxide layer 103 and converts the insulator to a semiconductor or conductor.

公开(公告)号：JPH11307738A

公开(公告)日：1999-11-05

申请号：JP23905598

申请日：1998-08-25

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  SHA BUNEKI ,  YEW TRI-RUNG

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To form a plurality of gates, a common source/drain region and a source/drain region on a substrate by a method wherein a self-alignment contact window to be opened (hereinafter, a PSACW) is formed and a part of the common source/drain region is exposed. SOLUTION: After a source/drain 210 and a common source/drain region 210a are sufficiently formed, an insulation film 212 is formed on a substrate 200 and a gate 202. By using self-alignment technology, a PSACW 211 is formed in the insulation film 212, which becomes an insulation film 202a. By using this technology in order to form a PASCW 211, an etching process can be simply performed and a manufacture can be simplified more. Further, a sidewall having the inclined PACW 211 is provided with a larger region, and the PASCW can store greater electric charges.

公开(公告)号：JPH11307447A

公开(公告)日：1999-11-05

申请号：JP14873298

申请日：1998-05-29

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KYU SHIKUN ,  RI RITSUCHU ,  KO ISEI ,  TEI EIMEI

IPC: G03F7/22 ,  G03F7/20 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To provide a coolant container which prevents leakage of coolant. SOLUTION: The coolant container has a storage container 30 for storing coolant, a tubular projection on a top part of the storage container 30 which runs along a central line thereof to form an inlet for coolant and has a hollow part passing through the storage container 30 and a screw.cap 32 having a male screw thread which engages with a male screw thread of the tube for closing the coolant inlet airtightly in an inner circumferential part. The container is a closed system except a coolant inlet, a circulation output duct and a circulation input duct. Consequently, it is possible to eliminate a fault regarding airtightness of a conventional coolant container and to prevent leakage of coolant. As a result, it is possible to prevent shortage of an amount of coolant of a stepper which generates various problems in a stepper and breaks a stepper.