公开(公告)号：KR1020100058909A

公开(公告)日：2010-06-04

申请号：KR1020080117494

申请日：2008-11-25

Applicant: 삼성전자주식회사

Inventor： 임동현 ,  안형근 ,  조성래 ,  김익수

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1683 ,  H01L45/143

Abstract: PURPOSE: A method of forming resistance changeable memory device is provided to form a variable resistance film with an opening filled with the amorphous state by forming an opening in an insulation film on a substrate. CONSTITUTION: A first mold dielectric film(120) including a first trench(123) is formed on a substrate(110). An opening(143) is formed within the first mold dielectric film. The variable resistance film filling the opening is formed. The variable resistance film comprises the antimony-telenium compound in which antimony is abundant. The variable resistance film is filled with the amorphous state within opening.

Abstract translation: 目的：提供一种形成电阻变化记忆装置的方法，通过在基板上的绝缘膜上形成开口来形成具有填充有非晶状态的开口的可变电阻膜。 构成：在基板（110）上形成包括第一沟槽（123）的第一模具电介质膜（120）。 在第一模具电介质膜内形成开口（143）。 形成填充开口的可变电阻膜。 可变电阻膜包括其中锑丰富的锑 - 硒化合物。 可变电阻膜在开口内充满无定形状态。

公开(公告)号：KR1020100041139A

公开(公告)日：2010-04-22

申请号：KR1020080100174

申请日：2008-10-13

Applicant: 삼성전자주식회사

Inventor： 오규환 ,  안형근 ,  박순오 ,  안동호 ,  박영림

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/141 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666 ,  H01L45/1683 ,  H01L21/31051 ,  H01L21/76229 ,  H01L45/143

Abstract: PURPOSE: A memory for manufacturing a multi-level cell for storing multiple bits data in one memory cell using a phase change material with three or more parallel structures is provided to identify resistance values by differentiating set resistance values based on the composition ratio and the kinds of the phase change material. CONSTITUTION: Three or more lower electrodes(220, 222, 224) are parallely formed on a contact plug(210). Three or more phase change materials(330, 332, 334) are parallely formed on the lower electrodes. The phase change materials correspond to the lower electrodes. An upper electrode is formed on the phase change materials. A part of the upper part of the lower electrodes is removed. The phase change materials are embedded in the removed space.

Abstract translation: 目的：提供一种用于使用具有三个或更多个并联结构的相变材料将多位数据存储在一个存储单元中的多级单元的存储器，以通过基于组成比和类型来区分设定电阻值来识别电阻值 的相变材料。 构成：三个或更多个下电极（220,222,224）平行地形成在接触插塞（210）上。 三个或更多个相变材料（330,332,334）平行地形成在下电极上。 相变材料对应于下部电极。 在相变材料上形成上电极。 去除下部电极的上部的一部分。 相变材料嵌入在移除的空间中。

公开(公告)号：KR100953960B1

公开(公告)日：2010-04-21

申请号：KR1020080029249

申请日：2008-03-28

Applicant: 삼성전자주식회사

Inventor： 박정희 ,  하용호 ,  안형근 ,  박준상 ,  권현숙 ,  강명진 ,  박두환

IPC: H01L21/28

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1666

Abstract: A contact structure that includes a first pattern formed on a substrate, wherein the first pattern has a recessed region in an upper surface thereof, a planarized buffer pattern formed on the first pattern, and a conductive pattern formed on the planarized buffer pattern.

公开(公告)号：KR1020090111742A

公开(公告)日：2009-10-27

申请号：KR1020080092855

申请日：2008-09-22

Applicant: 삼성전자주식회사

Inventor： 안형근 ,  김난영 ,  윤순길

IPC: H01L21/20 ,  H01L27/115

CPC classification number: C23C16/305 ,  H01L21/20 ,  H01L45/141

Abstract: PURPOSE: A method of forming chalcogenide thin film and a method of manufacturing a memory device using the same are provided to successively supply the tellurium and antimony source to a germanium thin film. CONSTITUTION: A method of forming chalcogenide thin film is as follows. The germanium thin film is formed by supplying the first antimony source and the germanium source to the top of the substrate(S120). The germanium thin film is grown to the multi-component system thin film by supplying the tellurium source or the second antimony source to the germanium thin film(S130). The first antimony source promotes the growth of the germanium thin film(S140).

Abstract translation: 目的：提供一种形成硫族化物薄膜的方法和使用其制造存储器件的方法，以将碲和锑源连续供应至锗薄膜。 构成：形成硫族化物薄膜的方法如下。 通过将第一锑源和锗源供给到基板的顶部而形成锗薄膜（S120）。 通过向锗薄膜供给碲源或第二锑源，将锗薄膜生长至多组分体系薄膜（S130）。 第一锑源促进锗薄膜的生长（S140）。

公开(公告)号：KR1020080099459A

公开(公告)日：2008-11-13

申请号：KR1020070045014

申请日：2007-05-09

Applicant: 삼성전자주식회사

Inventor： 안형근 ,  안동호 ,  호리이히데키 ,  고한봉 ,  박영림

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/76877 ,  H01L21/28273 ,  H01L21/31144 ,  H01L21/67075

Abstract: A data store layer pattern having the small width than 100nm in the forming process can be not damaged, and the data store layer pattern can be steadily molded. Accordingly, the reliability and performance characteristic of the memory device including data store layer pattern can be improved. The first insulating layer(120) including the first conductive pattern(125) on the substrate(110) is formed. The laminated data store layer pattern(135), and the second conductive pattern(145) and sacrificial layer pattern are formed on the first conductive pattern. The second insulating layer(160) is formed on the sacrificial layer pattern. The second insulating layer is patterned and then the first hole to expose the sacrificial layer pattern is formed. The sacrificial layer pattern is removed, and then the second hole to expose the second conductive pattern is formed. The third conductive pattern(190) connected to the second conductive pattern within the first and second holes is formed.

Abstract translation: 在成形过程中，具有小于100nm的宽度的数据存储层图案可以不被损坏，并且可以稳定地模制数据存储层图案。 因此，可以提高包括数据存储层图案的存储装置的可靠性和性能特性。 形成包括在基板（110）上的第一导电图案（125）的第一绝缘层（120）。 层压数据存储层图案（135）和第二导电图案（145）以及牺牲层图案形成在第一导电图案上。 第二绝缘层（160）形成在牺牲层图案上。 图案化第二绝缘层，然后形成用于露出牺牲层图案的第一孔。 去除牺牲层图案，然后形成第二孔以露出第二导电图案。 形成连接到第一和第二孔内的第二导电图案的第三导电图案（190）。

公开(公告)号：KR100819560B1

公开(公告)日：2008-04-08

申请号：KR1020070029280

申请日：2007-03-26

Applicant: 삼성전자주식회사

Inventor： 안형근 ,  호리이히데끼 ,  신종찬 ,  안동호 ,  배준수 ,  박정희

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/2463 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683 ,  H01L45/141

Abstract: A phase change memory device and a method for manufacturing the same are provided to minimize thermal interference between phase change patterns by increasing transfer paths with respect to heat generated in an interface between a first surface and a first phase change pattern and transferred to a second phase change pattern. A first electrode(71) having a first surface(S1) is arranged on a substrate. A second electrode(72) has a second surface(S2) located at another level with respect to the first surface. The second electrode is separated from the first electrode. A first phase change pattern(77) is contacted to the first surface. A second phase change pattern(78) is contacted to the second surface. An interlayer dielectric(57) is arranged on the substrate and has first and second contact holes(61,62). The first surface and the first phase change pattern are arranged in the first contact hole. The second surface and the second phase change pattern are arranged in the second contact hole.

Abstract translation: 提供了一种相变存储器件及其制造方法，用于通过增加相对于在第一表面和第一相变图案之间的界面中产生的热而传递到第二相位的传递路径来最小化相变图案之间的热干扰 改变模式 具有第一表面（S1）的第一电极（71）布置在基板上。 第二电极（72）具有相对于第一表面位于另一个水平的第二表面（S2）。 第二电极与第一电极分离。 第一相变图案（77）与第一表面接触。 第二相变图案（78）与第二表面接触。 层间电介质（57）布置在衬底上并具有第一和第二接触孔（61,62）。 第一表面和第一相变图案布置在第一接触孔中。 第二表面和第二相变图案布置在第二接触孔中。

公开(公告)号：KR100711517B1

公开(公告)日：2007-04-27

申请号：KR1020060033239

申请日：2006-04-12

Applicant: 삼성전자주식회사

Inventor： 신희주 ,  신종찬 ,  박순오 ,  안형근 ,  고한봉

IPC: H01L21/8247 ,  H01L27/115

公开(公告)号：KR1020040041329A

公开(公告)日：2004-05-17

申请号：KR1020020069541

申请日：2002-11-11

Applicant: 삼성전자주식회사

Inventor： 안형근 ,  이상우 ,  김형준

IPC: H01L27/105

CPC classification number: H01L28/75 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

Abstract: PURPOSE: A ferroelectric capacitor and a manufacturing method thereof are provided to be capable of increasing the efficient surface area of a ferroelectric layer. CONSTITUTION: A ferroelectric capacitor is provided with a semiconductor substrate(100), a support insulation layer(160) formed at the upper portion of the semiconductor substrate, a lower electrode(280a) for filling a trench(200) of the support insulating layer, and a seed conductive layer(300a) for partially enclosing the lower electrode. The ferroelectric capacitor further includes a ferroelectric layer(320) formed on the entire surface of the resultant structure and an upper electrode(340a) formed on the predetermined portion of the ferroelectric layer. Preferably, the lower electrode is higher than the support insulation layer and the seed conductive layer completely encloses the lower electrode protruded from the support insulation layer.

Abstract translation: 目的：提供一种强电介质电容器及其制造方法，能够提高铁电体层的有效表面积。 构成：铁电电容器设置有半导体衬底（100），形成在半导体衬底的上部的支撑绝缘层（160），用于填充支撑绝缘层的沟槽（200）的下电极（280a） ，以及用于部分封装下电极的种子导电层（300a）。 铁电电容器还包括形成在所得结构的整个表面上的铁电层（320）和形成在铁电体层的预定部分上的上电极（340a）。 优选地，下电极高于支撑绝缘层，并且种子导电层完全包围从支撑绝缘层突出的下电极。

公开(公告)号：KR1020020013154A

公开(公告)日：2002-02-20

申请号：KR1020000046615

申请日：2000-08-11

Applicant: 삼성전자주식회사

Inventor： 조학주 ,  안형근

IPC: H01L27/108

CPC classification number: H01L27/11502 ,  H01L28/55

Abstract: PURPOSE: A memory device having a capacitor encapsulated by a multilayer including a dual layer composed of the same material is provided to control deterioration of a dielectric layer of the capacitor, by using an encapsulation layer composed of a passivation layer and a blocking layer which are composed of the same material. CONSTITUTION: The capacitor has a lower electrode(34), an upper electrode(38) and the dielectric layer(36) interposed between the lower electrode and the upper electrode. A multilayered encapsulation layer includes the first blocking layer(48) and the first passivation layer(42) formed on the first blocking layer, surrounding the capacitor and composed of the same material.

Abstract translation: 目的：提供一种具有由包括由相同材料构成的双层的多层封装的电容器的存储器件，以通过使用由钝化层和阻挡层构成的封装层来控制电容器的电介质层的劣化， 由相同的材料组成。 构成：电容器具有下电极（34），上电极（38）和介电层（36），介于下电极和上电极之间。 多层封装层包括形成在第一阻挡层上的第一阻挡层（48）和第一钝化层（42），其围绕电容器并由相同的材料构成。

公开(公告)号：KR100203059B1

公开(公告)日：1999-06-15

申请号：KR1019970001047

申请日：1997-01-15

Applicant: 삼성전자주식회사

Inventor： 권순구 ,  안형근

IPC: H02H7/20

Abstract: 본 발명은 셋 ESD 보호 회로에 관한 것으로, 메인 파워 입력단에 연결되고, 전원단자로부터 상기 메인 파워 입력단에 입력되는 순간 고전압을 디스챠징시키는 제 1 디스챠지 수단과, 전원단자로부터 상기 메인 파워 입력단에 입력되는 상기 순간 고전압이 상기 메인 파워 입력단에 순간 입력되는 것을 방지하는 제 2 디스챠지 수단과, 전원단자로부터 소정의 전압을 입력받고, 이 전압이 일정 전압 이상이 되었을 때, 상기 제 1 디스챠지 수단을 구동시키는 디스챠지 구동회로부를 포함하여, 수천 또는 수만 볼트 이상의 전압이 순간적으로 셋에 가해졌을 때 셋을 안정적으로 보호할 수 있고, 셋의 동작 기능에 이상이 없도록 할 수 있으며, 셋 ESD의 기능을 향상시킬 수 있다.