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公开(公告)号：KR1020050097085A
公开(公告)日：2005-10-07
申请号：KR1020040021812
申请日：2004-03-30
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L21/336
Abstract: 본 발명은 이온화 충돌을 이용한 반도체 소자 및 그 제조방법에 관한 것으로, 본 발명에 따른 반도체 소자는 계단 형상의 반도체기판과; 상기 반도체기판의 돌출된 일단에 형성된 소스 영역과; 상기 소스 영역 상부에 형성된 마스크층과; 상기 소스 영역의 일측면과 상기 반도체기판의 타단 상부 전면에 형성된 게이트 절연막과; 상기 게이트 절연막 상부 꺾인 부위에 형성된 측벽 게이트와; 상기 반도체기판의 타단에 일정 길이의 진성영역을 구현하기 위해 상기 측벽 게이트 및 상기 게이트 절연막의 상부에 형성된 제 1 절연막 측벽과; 상기 제 1 절연막 측벽의 가장자리에 맞추어 상기 반도체기판의 타단 일면적 밑에 형성된 드레인 영역으로 구성된 것으로서, 종래의 반도체 소자와 달리 소스 또는 드레인 중 어느 하나의 영역이 돌출되고 측벽 게이트를 이용하기 때문에 제조공정을 간단히 할 수 있으며, 게이트, 소스/드레인, 채널 및 진성영역이 자기 정렬되어 형성되며, 기생성분이 억제되어 소자의 성능을 향상시킬 수 있고, 궁극적으로는 소자의 축소화가 용이한 장점이 있다.
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公开(公告)号：KR100467527B1
公开(公告)日：2005-01-24
申请号：KR1020010035456
申请日：2001-06-21
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/78
Abstract: PURPOSE: A metal oxide semiconductor field effect transistor(MOSFET) with a dual gate is provided to reduce contact resistance between polycrystalline silicon and a pin, by using a monocrystalline silicon portion on a buried oxide layer of a silicon-on-insulator(SOI) substrate. CONSTITUTION: An insulator is formed on a semiconductor substrate(10). A source region and a drain region are formed on the insulator, composed of monocrystalline silicon and separated from each other while an area lies between the source region and the drain region. A channel formed of monocrystalline silicon is formed on the insulator, crossing a part of the area and connecting the source region with the drain region. An insulation layer is formed on the channel. A gate is formed on the area between the source region and the drain region, surrounding the channel, both side surfaces of the insulation layer and the upper portion of the insulation layer. A gate insulation layer(15,15') is formed between the gate and the source/drain region to make the gate independent of the source/drain region electrically.
Abstract translation: 目的：通过在绝缘体上硅（SOI）的掩埋氧化物层上使用单晶硅部分，提供具有双栅极的金属氧化物半导体场效应晶体管（MOSFET）以减少多晶硅与引脚之间的接触电阻。 基质。 构成：绝缘体形成在半导体衬底（10）上。 源极区域和漏极区域形成在绝缘体上，由单晶硅构成并且彼此分离，而区域位于源极区域和漏极区域之间。 在绝缘体上形成由单晶硅形成的沟道，该沟道与区域的一部分交叉并且将源极区域与漏极区域连接。 通道上形成绝缘层。 栅极形成在源极区和漏极区之间的区域上，围绕沟道，绝缘层的两侧表面和绝缘层的上部。 栅极绝缘层（15,15'）形成在栅极与源极/漏极区域之间以使栅极与源极/漏极区域电独立。
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公开(公告)号：KR1020040067047A
公开(公告)日：2004-07-30
申请号：KR1020030004002
申请日：2003-01-21
Applicant: 재단법인서울대학교산학협력재단 , 이진호
IPC: H01L29/786
Abstract: PURPOSE: An organic TFT and a fabricating method thereof are provided to form an organic semiconductor material layer having a large grain size by coating a diluted PMMA coating layer on a source electrode, a drain electrode, and a gate insulating layer and depositing an organic semiconductor material thereon. CONSTITUTION: An organic TFT includes a substrate, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, a diluted PMMA(Poly-Methyl-MethAcrylate) coating layer, and an organic semiconductor material. The gate electrode(20) is formed on the substrate(10). The gate insulating layer(30) is formed on the substrate in order to cover the gate electrode. The source electrode(51) and the drain electrode(52) are formed on the gate insulating layer. The diluted PMMA coating layer(60) is formed on the gate insulating layer in order to cover the source and the drain electrodes. The organic semiconductor material(80) is partially deposited on the source and the drain electrodes and the diluted PMMA coating layer.
Abstract translation: 目的：提供一种有机TFT及其制造方法，通过在源电极，漏电极和栅绝缘层上涂布稀薄的PMMA涂层，形成具有大晶粒尺寸的有机半导体材料层，并沉积有机半导体 材料上。 构成：有机TFT包括基板，栅电极，栅极绝缘层，源电极，漏电极，稀释的PMMA（聚甲基 - 甲基丙烯酸酯）涂层和有机半导体材料。 栅电极（20）形成在基板（10）上。 为了覆盖栅电极，在基板上形成栅绝缘层（30）。 源极电极（51）和漏电极（52）形成在栅极绝缘层上。 为了覆盖源极和漏极，在栅极绝缘层上形成稀释的PMMA被覆层（60）。 有机半导体材料（80）部分沉积在源电极和漏极电极和稀释的PMMA涂层上。
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公开(公告)号：KR1020040004916A
公开(公告)日：2004-01-16
申请号：KR1020020039146
申请日：2002-07-06
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L21/8244
CPC classification number: B82Y10/00 , H01L27/11 , H01L29/66439 , H01L29/66772 , H01L29/7613 , H01L29/78654 , Y10S438/962
Abstract: PURPOSE: A method for fabricating a semiconductor device with negative differential conductivity is provided to embody a tunneling device according to an applied voltage and a semiconductor device having negative differential conductivity at a room temperature by including a channel region with a high impurity density and a channel with length and width of several tens of nanometer. CONSTITUTION: A single crystalline silicon layer of a silicon-on-insulator(SOI) substrate composed of a silicon support member(31), a buried oxide layer(32) and the single crystalline silicon layer is etched to form a source region and a drain region that are isolated from each other. The channel region having a fine line width is connected to the source/drain region. Ions are implanted into the upper portion of the source region, the channel region and the drain region to implant impurities into the channel region, having a density higher than an effective density state in which electrons or holes can exist. The first insulation layer is formed on the source region, the channel region, the drain region and the buried oxide layer and is etched to form a sidewall spacer(39) on the sidewall of the source region, the channel region and the drain region. The second insulation layer is formed. A gate insulation layer is formed on the channel region. A gate material is deposited and etched to form a gate(37) of a fine line width in a direction vertical to the channel region. Impurity ions of different conductivity from that of the abovementioned ions are implanted into the source/drain region.
Abstract translation: 目的：提供一种用于制造具有负差分导电率的半导体器件的方法，以通过包括具有高杂质密度的沟道区和沟道来实现根据施加电压的隧道装置和在室温下具有负差分导电率的半导体器件 长度和宽度几十纳米。 构成：蚀刻由硅支撑构件（31），掩埋氧化物层（32）和单晶硅层构成的绝缘体上硅（SOI）衬底的单晶硅层，以形成源区和 漏极区域彼此隔离。 具有细线宽度的沟道区域连接到源极/漏极区域。 离子被注入到源极区域，沟道区域和漏极区域的上部，以将杂质植入沟道区域，其密度高于存在电子或空穴的有效密度状态。 第一绝缘层形成在源极区域，沟道区域，漏极区域和掩埋氧化物层上，并被蚀刻以在源极区域，沟道区域和漏极区域的侧壁上形成侧壁间隔物（39）。 形成第二绝缘层。 在沟道区上形成栅极绝缘层。 沉积并蚀刻栅极材料以在垂直于沟道区的方向上形成细线宽度的栅极（37）。 与上述离子的导电性不同的杂质离子注入源/漏区。
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公开(公告)号：KR100396137B1
公开(公告)日：2003-08-27
申请号：KR1020010033065
申请日：2001-06-13
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L21/027
Abstract: PURPOSE: A method for forming ultra-fine multi-patterns is provided to obtain the ultra-fine multi-patterns of a desired size in a narrow interval by performing a multiple patterning process using a sidewall. CONSTITUTION: A pattern layer, the second pattern layer, and the first pattern layer are sequentially deposited on a substrate. The first pattern is formed on the first pattern layer. The first sidewall layer is deposited on the first pattern. A sidewall is formed by performing a dry etch process. The second pattern is formed by etching the second pattern layer. The sidewall is removed from the second pattern. The second sidewall layer is deposited on the second pattern. The second sidewall(22') is formed by performing the dry etch process. A pattern(P) is formed by etching the pattern layer.
Abstract translation: 目的：提供一种形成超精细多图案的方法，以通过使用侧壁执行多重图案化工艺来以窄间隔获得期望尺寸的超精细多图案。 构成：图案层，第二图案层和第一图案层依次沉积在基底上。 第一图案形成在第一图案层上。 第一侧壁层沉积在第一图案上。 通过执行干蚀刻工艺形成侧壁。 第二图案通过蚀刻第二图案层而形成。 侧壁从第二图案移除。 第二侧壁层沉积在第二图案上。 第二侧壁（22'）通过执行干式蚀刻工艺而形成。 通过蚀刻图案层形成图案（P）。
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Patent Agency Ranking
公开(公告)号：KR1020020068801A
公开(公告)日：2002-08-28
申请号：KR1020010009078
申请日：2001-02-22
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/78
Abstract: PURPOSE: A field effect transistor and a method for fabricating the same are provided to use a shallow electronic layer excited by a field effect as a source/drain region. CONSTITUTION: A gate insulating layer(2) is formed on a semiconductor substrate(1) by growing an oxide layer. A side gate material layer is formed by depositing and doping a polysilicon on the gate insulating layer(2). The side gate material layer is patterned. A source/drain diffusion layer(4) is formed by implanting ions into the semiconductor substrate(1). A silicon nitride layer(5) is deposited on the patterned side gate material layer. A silicon oxide layer is formed on the side gate material layer and the silicon nitride layer(5). A silicon oxide layer sidewall(6) is formed by etching the silicon oxide layer. A couple of side gate(3) is formed by etching a side gate material layer. A main gate(7) is formed by depositing and doping the polysilicon.
Abstract translation: 目的：提供场效应晶体管及其制造方法，以使用由场效应激发的浅电子层作为源/漏区。 构成：通过生长氧化物层，在半导体衬底（1）上形成栅绝缘层（2）。 通过在栅极绝缘层（2）上沉积和掺杂多晶硅来形成侧栅极材料层。 侧栅材料层被图案化。 源极/漏极扩散层（4）通过将离子注入到半导体衬底（1）中而形成。 在图案化的侧栅极材料层上沉积氮化硅层（5）。 在侧栅材料层和氮化硅层（5）上形成氧化硅层。 通过蚀刻氧化硅层形成氧化硅层侧壁（6）。 通过蚀刻侧栅材料层形成一对侧栅（3）。 通过沉积和掺杂多晶硅形成主栅极（7）。
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公开(公告)号：KR1020140074722A
公开(公告)日：2014-06-18
申请号：KR1020120142998
申请日：2012-12-10
Applicant: 삼성전자주식회사 , 서울대학교산학협력단
Abstract: The present invention relates to a semiconductor light emitting device, which comprises a first conductive semiconductor layer; an active layer formed on the first conductive semiconductor layer; a second conductive semiconductor layer formed on the active layer and having an upper surface on which at least one groove unit is formed; a transparent electrode layer formed on the second conductive semiconductor layer; and a first electrode and a second electrode electrically connected to the first conductive semiconductor layer and the second conductive semiconductor layer, wherein the center of the groove unit intersects with a straight line which links the center of the first electrode and the center of the second electrode to improve the current distribution, thereby improving the internal light extraction efficiency.
Abstract translation: 本发明涉及一种半导体发光器件，其包括第一导电半导体层; 形成在所述第一导电半导体层上的有源层; 形成在所述有源层上并具有上表面的第二导电半导体层，所述上表面上形成有至少一个沟槽单元; 形成在所述第二导电半导体层上的透明电极层; 以及电连接到第一导电半导体层和第二导电半导体层的第一电极和第二电极，其中，沟槽单元的中心与连接第一电极的中心和第二电极的中心的直线相交 提高电流分布，从而提高内部光提取效率。
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公开(公告)号：KR101926356B1
公开(公告)日：2018-12-07
申请号：KR1020110129558
申请日：2011-12-06
Applicant: 삼성전자주식회사 , 서울대학교산학협력단
IPC: H01L29/78 , H01L21/336
Abstract: 기판 상에 백-바이어스 영역(back-bias region)이 배치된다. 상기 기판 및 상기 백-바이어스 영역을 덮는 매립 절연 막이 형성된다. 상기 매립 절연 막 상에 상기 백-바이어스 영역과 부분적으로 중첩된 바디(body)가 형성된다. 상기 바디(body)에 접촉된 드레인(drain)이 배치된다. 상기 바디(body)의 상면 및 측면을 덮는 게이트 전극이 배치된다.
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公开(公告)号：KR101878311B1
公开(公告)日：2018-07-17
申请号：KR1020110147035
申请日：2011-12-30
Applicant: 삼성전자주식회사 , 서울대학교산학협력단
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/6653 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
Abstract: 기판상에게이트전극을형성한다. 상기게이트전극의측면및 상기게이트전극에가까운(near) 상기기판상에제1 버퍼층, 제2 버퍼층, 및제3 버퍼층을형성한다. 상기제3 버퍼층은상기제2 버퍼층보다높은유전상수를갖는물질막이다. 상기제3 버퍼층 상에상기게이트전극의측면을덮는스페이서를형성한다. 상기게이트전극에가까운(near) 상기기판상에상기제3 버퍼층이노출된다. 상기노출된제3 버퍼층을제거하여상기기판상에상기제2 버퍼층을노출한다. 상기노출된제2 버퍼층을제거하여상기기판상에상기제1 버퍼층을노출한다. 상기스페이서를이온주입마스크로사용하여상기기판내에깊은접합(deep junction)을형성한다. 상기스페이서를제거한다. 상기스페이서를제거하는동안상기제1 버퍼층은상기깊은접합(deep junction) 상에보존된다. 상기스페이서는상기제3 버퍼층, 상기제2 버퍼층 및상기제1 버퍼층과다른물질막을갖는다.
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