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    Integrated semiconductor devices with amorphous silicon beam, methods of manufacture and design structure
    61.
    发明专利
    Integrated semiconductor devices with amorphous silicon beam, methods of manufacture and design structure 未知

    公开(公告)号：GB2510755A

    公开(公告)日：2014-08-13

    申请号：GB201408506

    申请日：2012-10-03

    Applicant: IBM

    Inventor： LUCE STEPHEN E ,  STAMPER ANTHONY K

    IPC: H03H3/02

    Abstract: Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS processes, methods of manufacture and design structures are disclosed. The method includes forming at least one beam (44) comprising amorphous silicon material (29) and providing an insulator material (32) over and adjacent to the amorphous silicon beam. The method further includes forming a via (50) through the insulator material and exposing a material (25) underlying the amorphous silicon beam (44). The method further includes providing a sacrificial material (36) in the via and over the amorphous silicon beam. The method further includes providing a lid (38) on the sacrificial material and over the insulator material. The method further includes venting, through the lid (vent hole 40), the sacrificial material and the underlying material to form an upper cavity (42a) above the amorphous silicon beam and a lower cavity (42b) below the amorphous silicon beam, respectively.

    Schaltbare Filter und Entwurfsstrukturen
    65.
    发明专利
    Schaltbare Filter und Entwurfsstrukturen 未知

    公开(公告)号：DE102013200215A1

    公开(公告)日：2013-07-25

    申请号：DE102013200215

    申请日：2013-01-10

    Applicant: IBM

    Inventor： CANDRA PANGLIJEN ,  DUNBAR THOMAS J ,  JAFFE MARK D ,  STAMPER ANTHONY K ,  WOLF RANDY L ,  GAMBINO JEFFREY P ,  ADKISSON JAMES W

    IPC: H03H9/64 ,  H01L41/08 ,  H03H3/08

    Abstract: Hierin werden schaltbare und/oder abstimmbare Filter, Herstellungsverfahren und Entwurfsstrukturen offenbart. Das Verfahren zum Bilden der Filter schließt das Bilden mindestens einer piezoelektrischen Filterstruktur ein, die eine Vielzahl von Elektroden aufweist, die auf einem piezoelektrischen Substrat gebildet sind. Das Verfahren schließt außerdem das Bilden einer feststehenden Elektrode mit einer Vielzahl von Fingern auf dem piezoelektrischen Substrat ein. Das Verfahren schließt zudem das Bilden einer beweglichen Elektrode mit einer Vielzahl von Fingern über dem piezoelektrischen Substrat ein. Das Verfahren schließt außerdem das Bilden von Betätigungselementen ein, die mit einem oder mehreren von der Vielzahl von Fingern der beweglichen Elektrode ausgerichtet sind.

    Strukturen mit mikroelektromechanischem System (MEMS) und Design-Strukturen
    66.
    发明专利
    Strukturen mit mikroelektromechanischem System (MEMS) und Design-Strukturen 未知

    公开(公告)号：DE102012223968A1

    公开(公告)日：2013-07-04

    申请号：DE102012223968

    申请日：2012-12-20

    Applicant: IBM

    Inventor： JAHNES CHRISTOPHER V ,  STAMPER ANTHONY K

    IPC: B81C1/00 ,  B81B3/00 ,  B81B7/02

    Abstract: Es werden Strukturen mit mikroelektromechanischem System (MEMS), Verfahren zur Herstellung und Designstrukturen offenbart. Das Verfahren beinhaltet das Bilden von wenigstens einer festen Elektrode auf einem Substrat. Das Verfahren beinhaltet des Weiteren das Bilden eines Arms eines mikroelektromechanischen Systems (MEMS) mit einer variierenden Breitenabmessung von einer Oberseite des MEMS-Arms aus gesehen über der wenigstens einen festen Elektrode.

    MEMS capacitor devices, capacitor trimming thereof and design structures
    67.
    发明专利
    MEMS capacitor devices, capacitor trimming thereof and design structures 未知

    公开(公告)号：GB2497649A

    公开(公告)日：2013-06-19

    申请号：GB201221916

    申请日：2012-12-05

    Applicant: IBM

    Inventor： STAMPER ANTHONY K ,  JAHNES CHRISTOPHER VINCENT

    IPC: B81C1/00 ,  B81B3/00 ,  H01G5/019 ,  H03H9/02

    Abstract: Micro-electro-mechanical structure (MEMS) capacitor devices, capacitor trimming for MEMS capacitor devices, and design structures are disclosed. The method includes identifying a process variation related to a formation of micro-electro­mechanical structure (MEMS) capacitor devices across a substrate. The method further includes providing design offsets or process offsets in electrode areas of the MEMS capacitor devices across the substrate, based on the identified process variation. This method compensates for the variance in capacitance during fabrication of the MEMS capacitors across an array of capacitors on a single substrate.

    MEMS composite beam
    68.
    发明专利
    MEMS composite beam 未知

    公开(公告)号：GB2497641A

    公开(公告)日：2013-06-19

    申请号：GB201221473

    申请日：2012-11-29

    Applicant: IBM

    Inventor： DEMUYNCK DAVID ALAN ,  CZABAJ BRIAN MATTHEW ,  STAMPER ANTHONY K

    IPC: B81C1/00 ,  H01H1/00

    Abstract: The composite beam 34 comprises multiple layers of metal and metal oxide. A single anisotropic reactive ion etch step is used to ensure that the edges of the beam layers are self aligned. Sacrificial oxide material 44 from around the beam is removed via the vent 48 using HF or xenon difluoride etchant. The MEMS beam may be used in a MEMS switch for mode switching of power amplifiers or analogue and mixed signal applications.

    Through silicon via lithographic alignment and registration
    69.
    发明专利
    Through silicon via lithographic alignment and registration 未知

    公开(公告)号：GB2489859A

    公开(公告)日：2012-10-10

    申请号：GB201212589

    申请日：2011-01-12

    Applicant: IBM

    Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    IPC: H01L21/768

    Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

    Buried metal dual damascene plate capacitor
    70.
    发明专利
    Buried metal dual damascene plate capacitor 未知

    公开(公告)号：GB2366077A

    公开(公告)日：2002-02-27

    申请号：GB0105197

    申请日：2001-03-02

    Applicant: IBM

    Inventor： GEFFKEN ROBERT M ,  STAMPER ANTHONY K

    IPC: H01L21/02 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L29/92

    Abstract: A metal capacitor is formed as part of metal dual damascene process in the making of a wafer. A lower plate (27) of the capacitor is sandwiched between an insulating layer (25) and a dielectric layer (29). The insulating layer on an opposite side abuts a layer of metallization (23, 24) and the dielectric layer separates the lower plate of the capacitor from an upper plate (59) of the capacitor. A portion (27A) of the lower plate projects into a via (37) adjacent to it that is filled with copper (63) and possibly a barrier layer (51A). The via projects up to a common surface with the upper plate but is electrically isolated from the upper plate. The via also extends down to the layer of metallization. The capacitor may include a high-k dielectric. Methods of making the capacitor are described.

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