中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

85 records (took 0.023 seconds)

    64.
    发明专利
    未知

    公开(公告)号：DE10128481B4

    公开(公告)日：2004-01-08

    申请号：DE10128481

    申请日：2001-06-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOLDBACH MATTHIAS ,  SELL BERNHARD ,  HECHT THOMAS

    IPC: B44C1/22 ,  C03C25/68 ,  G03F7/26 ,  H01L21/308 ,  H01L21/31

    Abstract: An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed and, on the basis of a reflective layer which is located under the photoresist layer, additionally exposed areas are exposed completely. In consequence, a first etching mask which is used for etching a substrate can be renewed by a second etching mask in that a photoresist layer which is applied to the first etching mask or instead of the first etching mask is exposed such that areas which have been exposed once are not yet completely exposed, and areas which have been additionally exposed on the basis of a reflective layer which is located under the photoresist layer and corresponds to the first etching mask are exposed completely.

    69.
    发明专利
    未知

    公开(公告)号：DE10326805B4

    公开(公告)日：2007-02-15

    申请号：DE10326805

    申请日：2003-06-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOLDBACH MATTHIAS ,  MIKOLAJICK THOMAS ,  BIRNER ALBERT

    IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788

    Abstract: Silicon nanocrystals are applied as storage layer ( 6 ) and removed using spacer elements ( 11 ) laterally with respect to the gate electrode ( 5 ). By means of an implantation of dopant, source/drain regions ( 2 ) are fabricated in a self-aligned manner with respect to the storage layer ( 6 ). The portions of the storage layer ( 6 ) are interrupted by the gate electrode ( 5 ) and the gate dielectric ( 4 ), so that a central portion of the channel region ( 3 ) is not covered by the storage layer ( 6 ). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.

    70.
    发明专利
    未知

    公开(公告)号：DE10333777B4

    公开(公告)日：2007-01-25

    申请号：DE10333777

    申请日：2003-07-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOLDBACH MATTHIAS

    IPC: H01L21/822 ,  H01L21/20 ,  H01L21/334 ,  H01L21/8232 ,  H01L21/8242 ,  H01L27/108

    Abstract: The present invention provides a method for fabricating a trench capacitor with an insulation collar ( 10; 10 a, 10 b) in a substrate ( 1 ), which is electrically connected to the substrate ( 1 ) on one side via a buried contact ( 15 a, 15 b; 70 ), having the steps of: providing a trench ( 5 ) in the substrate ( 1 ) using a hard mask ( 2, 3 ) with a corresponding mask opening; providing a capacitor dielectric ( 30 ) in the lower and central trench region, the insulation collar ( 10 ) in the central and upper trench region and an electrically conductive filling ( 20 ) in the lower and central trench region, the top side of the electrically conductive filling ( 20 ) being sunk in the upper trench region with respect to the top side of the substrate ( 1 ); providing a silicon nitride liner ( 40 ) above the hard mask ( 2, 3 ) and in the trench ( 5 ); providing a silicon liner ( 50 ) above the silicon nitride liner ( 40 ); carrying out an oblique implantation (I 1 ), as a result of which a shaded region ( 50 a) of the silicon liner ( 50 ) is made selectively removable with respect to the rest of the silicon liner ( 50 ) by means of an etching process; selectively removing the shaded region ( 50 a) of the silicon liner ( 50 ) by means of the etching process; oxidizing the rest of the silicon liner ( 50 ); carrying out a spacer etching at the oxidized rest of the silicon liner ( 50' ); and depositing and etching back a conductive filling ( 70 ) in order to form the buried contact.

Patent Agency Ranking