公开(公告)号：DE102005060365A1

公开(公告)日：2007-06-21

申请号：DE102005060365

申请日：2005-12-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WIESBAUER ANDREAS ,  CLARA MARTIN ,  WALTER SERGIO ,  POETSCHER THOMAS

IPC: H03F3/38

Abstract: The method involves comparing input signals applied to a pulse width modulator with a threshold value. The synchronization loop is controlled, when the input signal exceeds the threshold value, in such a manner that changes of phasing of output signals of the pulse width modulator and/or a signal source is not caused by the synchronization loop for a certain time period. The signal source includes another pulse width modulator. Independent claims are also included for the following: (1) a device for controlling excessive load of a synchronization loop (2) a synchronization loop for synchronization of output signals of pulse width modulator with output signal of a signal source.

公开(公告)号：DE102005052702A1

公开(公告)日：2007-05-10

申请号：DE102005052702

申请日：2005-11-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WIESBAUER ANDREAS ,  CLARA MARTIN ,  WALTER SERGIO ,  POETSCHER THOMAS

IPC: H03K7/08

公开(公告)号：DE102005028726A1

公开(公告)日：2007-01-04

申请号：DE102005028726

申请日：2005-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STRAEUSNIGG DIETMAR ,  GAGGL RICHARD ,  WIESBAUER ANDREAS

IPC: H03M3/00 ,  H03M1/12

Abstract: An analog-to-digital converter system converts an analog input signal into a digital output signal. The analog input signal is converted into a first digital signal by a fed back analog-to-digital conversion. A second digital signal is additionally formed, depending on the analog input signal or on the digital output signal, which, combined with the first digital signal, results in the digital output signal.

公开(公告)号：DE102004031447A1

公开(公告)日：2006-01-19

申请号：DE102004031447

申请日：2004-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GIANDOMENICO ANTONIO DI ,  WIESBAUER ANDREAS ,  CLARA MARTIN ,  KOLHAUPT KLAUS ,  PATON SUSANA

IPC: H03M3/00

Abstract: Scrambling devices (15) rotate the digital output signal of the sigma delta encoder (1) as a function of a computed current pointer. Pointer computation pipeline mechanisms (16) calculate the value of the current pointer P(n+1) as a function of a preceding pointer P(n) and preceding output data D(n). The preceding pointer and the preceding output data are delayed by at least one clock cycle. Preferably the current pointer is computed from the sum of the preceding pointer and preceding output data. Independent claims are included for : (1) a sigma-delta analog-digital converter for converting an applied analog input signal into digital output data; and (2) a method for calculating a current value pointer for a data-weighting device forming an average value within a sigma-delta analog-digital converter.

公开(公告)号：DE10342056B4

公开(公告)日：2005-11-10

申请号：DE10342056

申请日：2003-09-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GAGGL RICHARD ,  WIESBAUER ANDREAS ,  INVERSI MAURIZIO

IPC: G06F7/50 ,  H03K5/00 ,  H03K5/24 ,  H03K7/00 ,  H03M3/00 ,  H03M3/02

Abstract: Addition circuit comprises two capacitors (21,22) and switches (11,12) and is so set-up that, during first clock phase, each of signals (V1,2) to be added is stored in corresponding capacitor by its charging. During second clock phase, capacitors are parallel-connected by switches for charge equalising between capacitors. Thus after charge equalising, gradually diminishing voltage forms output signal of addition circuit, with voltage diminishing up to scaling factor corresponding to sum of signals to be added. Independent claims are included for sigma-delta modulator circuit.

公开(公告)号：DE10053914C2

公开(公告)日：2003-05-22

申请号：DE10053914

申请日：2000-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WIESBAUER ANDREAS ,  CLARA MARTIN ,  WEINBERGER HUBERT ,  FLEISCHHACKER CHRISTIAN

IPC: H03M1/66 ,  H03M1/70

Abstract: Digital/analog converter with programmable gain for converting a digital input signal (Dn) into an analog output signal, the digital/analog converter (1) having:a signal input (2) for applying the digital input signal (Dn)a reference current source (7) for generating a reference current (Irefphi), the current intensity of the reference current output by the reference current source (7) being adjustable via a setting terminal (4) of the digital/analog converter (1)current mirror circuits which mirror the generated reference current (Iref) with an associated current mirror ratio to form mirror currentsa controllable switching device (57), which switches through the mirror currents output by the current mirror circuits, in a manner dependent on the digital input signal (Dn) present at the signal input (2), to a summation current node (62) for generating a summation current (Isum) anda current/voltage converter (17) for converting the generated summation current (Isum) into a corresponding voltage (UA), which is output as an analog output signal via an analog signal output (3) of the digital/analog converter (1).

公开(公告)号：AU2001260173A1

公开(公告)日：2002-10-15

申请号：AU2001260173

申请日：2001-03-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WIESBAUER ANDREAS ,  CLARA MARTIN ,  POTSCHER THOMAS ,  WEINBERGER HUBERT ,  HAUPTMANN JORG ,  MAGESACHER THOMAS

IPC: H03M1/00 ,  H03M1/20 ,  H03M1/66 ,  H03M3/00 ,  H04B14/04 ,  H04B14/06

Abstract: The invention creates a method and a device for digitally transmitting analog signals, in which oversampling is performed in analog/digital and digital/analog converters. In this arrangement, a digital/analog conversion is performed which, in particular, is suitable for VDSL systems. A transmitted digital transmission signal (110) is supplied to a mixing unit (201) and in the mixing unit (201), a receive noise signal (211) applied to a receive noise source terminal (209) is superimposed on the digital transmission signal (110). An interpolation filter unit (203), in combination with a subsequent noise shaping device (205), provides an increase in the frequency bandwidth, resulting in suitable oversampling.

公开(公告)号：DE10048419A1

公开(公告)日：2002-04-18

申请号：DE10048419

申请日：2000-09-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CLARA MARTIN ,  WIESBAUER ANDREAS ,  STRAEUSNIGG DIETMAR

IPC: H03M1/06 ,  H03M1/12

Abstract: The device converts a defined frequency bandwidth analog input signal to an offset-free digital output signal with a subtraction amplifier (5) that amplifies the difference between an input signal and a control signal, an analogue to digital converter circuit (18) with high clock rate, a digital clamp circuit (24) for low pass filtering and a digital to analog converter circuit (49) for converting the filtered signal to the analog control signal Independent claims are also included for the following: a use of an analogue to digital converter with fully differential components and a use of the analogue to digital converter for converting an xSDL signal into a digital output signal.

公开(公告)号：DE10005497A1

公开(公告)日：2001-08-09

申请号：DE10005497

申请日：2000-02-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHENK HEINRICH ,  KRUEGER MARTIN ,  WIESBAUER ANDREAS

IPC: H04L27/233 ,  H04L27/38 ,  H04L27/22

Abstract: The invention relates to the digital demodulation of a quadrature amplitude- or phase-modulated signal (xE(t)), whereby said signal is sampled with a sampling frequency fs and A/D converted, which has the following relationship, (1) with the carrier frequency f0, whereby lambda is a whole number greater than or equal to zero. The multiplications of the sampled and A/D converted quadrature amplitude- or phase-modulated signal usually necessary for demodulation, with the signal (2) and the signal (3) can be easily performed, whereby the individual sample values of the quadrature amplitude- or phase-modulated signal are multiplied by the value -1, 0 or 1.

公开(公告)号：DE102014109908B4

公开(公告)日：2025-03-20

申请号：DE102014109908

申请日：2014-07-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARZEN STEFAN ,  FUELDNER MARC ,  JENKNER CHRISTIAN ,  WIESBAUER ANDREAS

IPC: B81B7/02 ,  B81B5/00 ,  H03F1/00 ,  H03H9/46 ,  H04R19/01 ,  H10D84/00

Abstract: Vorrichtung mit mikroelektromechanischem System (MEMS), die Folgendes aufweist:eine erste Platte (101),eine zweite Platte (105), die oberhalb der ersten Platte (101) angeordnet ist,eine erste bewegliche Platte (102), die zwischen der ersten Platte (101) und der zweiten Platte (105) angeordnet ist, undeine zweite bewegliche Platte (103), die zwischen der ersten beweglichen Platte (102) und der zweiten Platte (105) angeordnet ist, wobei die MEMS-Vorrichtung einen ersten Eingangs-/Ausgangsknoten, der mit der ersten Platte (101) gekoppelt ist, einen zweiten Eingangs-/Ausgangsknoten, der mit der zweiten Platte (105) gekoppelt ist, einen dritten Eingangs-/Ausgangsknoten, der mit der ersten beweglichen Platte (102) gekoppelt ist, und einen vierten Eingangs-/Ausgangsknoten, der mit der zweiten beweglichen Platte (103) gekoppelt ist, umfasst, wobei der erste Eingangs-/Ausgangsknoten ein anderer Eingangs-/Ausgangsknoten als der zweite Eingangs-/Ausgangsknoten ist, und wobei der dritte Eingangs-/Ausgangsknoten ein anderer Eingangs-/Ausgangsknoten als der vierte ist Eingangs-/Ausgangsknoten ist, wobei die erste bewegliche Platte (102) starr mit der zweiten beweglichen Platte (103) gekoppelt ist, wobei die erste bewegliche Platte (102) ausgelegt ist, um von kapazitivem Koppeln mit der zweiten beweglichen Platte (103) abgeschirmt zu sein.