公开(公告)号：GB2503829A

公开(公告)日：2014-01-08

申请号：GB201317160

申请日：2011-12-12

Applicant: INTEL CORP

Inventor： ADRIAN JESUS CORBAL SAN ,  TOLL BRET L ,  VALENTINE ROBERT C ,  WIEDEMEIER JEFFREY G ,  SAMUDRALA SRIDHAR ,  GIRKAR MILIND BABURAO ,  FORSYTH ANDREW THOMAS ,  OULD-AHMED-VALL ELMOUSTAPHA ,  BRADFORD DENNIS R ,  WU LISA K

IPC: G06F9/30 ,  G06F9/305

Abstract: Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a selector between the first and second operands and storage of the selected data elements into the destination at the corresponding position in the destination.

公开(公告)号：DE102010053967A1

公开(公告)日：2011-07-14

申请号：DE102010053967

申请日：2010-12-09

Applicant: INTEL CORP

Inventor： LOKTYUKHIN MAXIM ,  MAHURIN ERIC ,  TOLL BRET L ,  DIXON MARTIN G ,  MIRKES SEAN P ,  KREITZER DAVID L ,  EL MOUSTAPHA OULD-AHMED-VALL ,  GOPAL VINODH

IPC: G06F9/30 ,  G06F9/315 ,  G06F9/34

Abstract: Das Empfangen eines Befehls, der einen Quelloperanden und einen Zieloperanden anzeigt. Das Speichern eines Ergebnisses im Zieloperanden als Antwort auf den Befehl. Der Ergebnisoperand kann aufweisen: (1) einen ersten Bereich von Bits mit einem durch den Befehl explizit angegebenen ersten Ende, wobei jedes Bit im Wert mit einem Bit des Quelloperanden in einer entsprechenden Position identisch ist, und (2) einen zweiten Bereich von Bits, die alle einen gleichen Wert haben, unabhängig von den Werten der Bits des Quelloperanden in entsprechenden Positionen. Die Ausführung des Befehls kann abschließen, ohne den ersten Bereich des Ergebnisses relativ zu den Bits mit identischem Wert in den entsprechenden Positionen des Quelloperanden zu bewegen, unabhängig von der Position des ersten Bereichs von Bits im Ergebnis. Ausführungseinheiten, um solche Befehle auszuführen, Computersysteme, die Prozessoren aufweisen, um solche Befehle auszuführen, und ein maschinenlesbares Medium, das solch einen Befehl speichert, werden ebenfalls offenbart.

公开(公告)号：DE102010054267A1

公开(公告)日：2011-06-30

申请号：DE102010054267

申请日：2010-12-13

Applicant: INTEL CORP

Inventor： GOPAL VINODH ,  GUILFORD JAMES D ,  WOLRICH GILBERT M ,  FEGHALI WAJDI K ,  OZTURK ERDINC ,  DIXON MARTIN G ,  MIRKES SEAN P ,  TOLL BRET L ,  LOKTYUKHIN MAXIM ,  DAVIS MARK C ,  FARCY ALEXANDRE J

IPC: G06F9/315 ,  G06F9/30 ,  G06F9/318

Abstract: Ein Verfahren nach einem Aspekt der Erfindung kann den Empfang eines Drehbefehls umfassen. Der Drehbefehl kann einen Quellenoperanden und einen Drehungsbetrag angeben. Ein Ergebnis kann in einem durch den Drehbefehl angegebenen Zieloperanden gespeichert werden. Im Ergebnis kann der Quellenoperand um den Drehungsbetrag gedreht worden sein. Die Ausführung des Drehbefehls kann ohne Lesen eines Übertrags-F1ags abgeschlossen werden.

公开(公告)号：EP3238031A4

公开(公告)日：2018-06-27

申请号：EP15873977

申请日：2015-11-23

Applicant: INTEL CORP

Inventor： OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT ,  TOLL BRET L ,  CORBAL SAN ADRIAN JESUS ,  CHARNEY MARK J ,  GIRKAR MILIND B

IPC: G06F9/30 ,  G06F7/485 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30018 ,  G06F17/16

Abstract: In several embodiments, vector extensions to an instruction set architecture include instructions to perform saturated signed and unsigned integer additions. In one embodiment, a vector signed integer add with signed saturation is provided. In one embodiment, a vector unsigned integer add with unsigned saturation is provided. In one embodiment, packed doubleword and quadword integers are supported for both signed and unsigned instructions.

公开(公告)号：EP2798458A4

公开(公告)日：2017-05-17

申请号：EP11878673

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： TOLL BRET L ,  VALENTINE ROBERT ,  CORBAL SAN ADRIAN JESUS ,  OULD-AHMED-VALL ELMOUSTAPHA ,  CHARNEY MARK J

IPC: G06F9/06 ,  G06F9/30 ,  G06F13/14

CPC classification number: G06F9/30189 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30145

Abstract: Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second packed data operation mask having second packed data operation mask bits. Each packed data operation mask bit of first mask corresponds to a packed data operation mask bit of second mask in corresponding position. Modify first flag to first value if bitwise AND of each packed data operation mask bit of first mask with each corresponding packed data operation mask bit of second mask is zero. Otherwise modify first flag to second value. Modify second flag to third value if bitwise AND of each packed data operation mask bit of first mask with bitwise NOT of each corresponding packed data operation mask bit of second mask is zero. Otherwise modify second flag to fourth value.

Abstract translation: 接收指示具有第一打包数据操作掩码位的第一打包数据操作掩码和具有第二打包数据操作掩码位的第二打包数据操作掩码的打包数据操作掩码比较指令。 第一掩码的每个打包数据操作掩码位对应于对应位置中的第二掩码的打包数据操作掩码位。 如果第一掩码的每个打包数据操作掩码位与​​第二掩码的每个对应打包数据操作掩码位的按位“与”为零，则将第一标志修改为第一值。 否则，修改第一个标志为第二个值。 如果第一掩码的每个打包数据操作掩码比特与第二掩码的每个对应打包数据操作掩码比特的比特不为“0”，则将第二标志修改为第三值。 否则，修改第二个标志为第四个值。

公开(公告)号：EP2798464A4

公开(公告)日：2016-08-17

申请号：EP11878881

申请日：2011-12-30

Applicant: INTEL CORP

Inventor： OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT ,  CORBAL SAN ANDRIAN JESUS ,  SAIR SULEYMAN ,  TOLL BRET L ,  SPERBER ZEEV ,  GRADSTEIN AMIT ,  RUBENSTEIN ASAF

IPC: G06F9/06 ,  G06F9/30 ,  G06F13/14

CPC classification number: G06F9/30032 ,  G06F9/30036

Abstract: A method of an aspect includes receiving a masked packed rotate instruction. The instruction indicates a first source packed data including a plurality of packed data elements, a packed data operation mask having a plurality of mask elements, at least one rotation amount, and a destination storage location. A result packed data is stored in the destination storage location in response to the instruction. The result packed data includes result data elements that each correspond to a different one of the mask elements in a corresponding relative position. Result data elements that are not masked out by the corresponding mask element include one of the data elements of the first source packed data in a corresponding position that has been rotated. Result data elements that are masked out by the corresponding mask element include a masked out value. Other methods, apparatus, systems, and instructions are disclosed.

公开(公告)号：EP2798466A4

公开(公告)日：2016-07-06

申请号：EP11878891

申请日：2011-12-30

Applicant: INTEL CORP

Inventor： ANDERSON CRISTINA S ,  TOLL BRET L ,  VALENTINE ROBERT ,  RUBANOVICH SIMON ,  GRADSTEIN AMIT

IPC: G06F9/30 ,  G06F7/499

CPC classification number: G06F9/3001 ,  G06F7/483 ,  G06F7/49947 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013

Abstract: A method of an aspect includes receiving a floating point round-off amount determination instruction. The instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point, and indicates a destination storage location. A result including one or more result floating point data elements is stored in the destination storage location in response to the floating point round-off amount determination instruction. Each of the one or more result floating point data elements includes a difference between a corresponding floating point data element of the source in a corresponding position, and a rounded version of the corresponding floating point data element of the source that has been rounded to the indicated number of the fraction bits. Other methods, apparatus, systems, and instructions are disclosed.

Abstract translation: 一种方面的方法包括接收浮点舍入量确定指令。 该指令指示一个或多个浮点数据元素的源，指示小数点之后的小数位数，并指示目的地存储位置。 包括一个或多个结果浮点数据元素的结果响应于浮点舍入量确定指令被存储在目的地存储位置中。 一个或多个结果浮点数据元素中的每一个包括相应位置中的源的对应浮点数据元素与已被舍入到指示的源的相应浮点数据元素的舍入版本之间的差 小数位数。 公开了其它方法，装置，系统和指令。

公开(公告)号：EP2798480A4

公开(公告)日：2016-06-29

申请号：EP11879023

申请日：2011-12-30

Applicant: INTEL CORP

Inventor： SAIR SULEYMAN ,  OULD-AHMED-VALL ELMOUSTAPHA ,  YOUNT CHARLES R ,  DOSHI KSHITIJ A ,  TOLL BRET L

IPC: G06F9/30 ,  G06F9/305 ,  H03M7/46

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/3016 ,  H03M7/46 ,  H03M7/6005

Abstract: A processor core that includes a hardware decode unit to decode a vector frequency compress instruction that includes a source operand and a destination operand. The source operand specifying a source vector register that includes a plurality of source data elements including one or more runs of identical data elements that are each to be compressed in a destination vector register as a value and run length pair. The destination operand identifies the destination vector register. The processor core also includes an execution engine unit to execute the decoded vector frequency compress instruction which causes, for each source data element, a value to be copied into the destination vector register to indicate that source data element's value. One or more runs of the source data elements equal are encoded in the destination vector register as the predetermined compression value followed by a run length for that run.

Abstract translation: 一种处理器核心，其包括用于解码包括源操作数和目的地操作数的向量频率压缩指令的硬件解码单元。 源操作数指定源向量寄存器，其包括多个源数据元素，其包括在目的地向量寄存器中作为值和游程长度对而被压缩的相同数据元素的一个或多个游程。 目标操作数标识目标向量寄存器。 处理器核心还包括执行引擎单元，用于执行解码的向量频率压缩指令，其对于每个源数据元素，其将被复制到目的地向量寄存器中的值指示源数据元素的值。 源数据元素相等的一个或多个运行在目标向量寄存器中被编码为预定压缩值，后跟该运行的运行长度。