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公开(公告)号：DE69222712D1
公开(公告)日：1997-11-20
申请号：DE69222712
申请日：1992-07-21
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , OLIVO MARCO
IPC: G11C11/417 , G11C7/06 , G11C16/06 , G11C16/28 , G11C17/00
Abstract: The discriminating sensitivity of a sense amplifier and the speed of the circuit are increased by exploiting the difference of potential which develops across the output nodes of the two control circuits, employed for enabling/disabling current paths of the input network of the differential amplifier, as a virtual additional signal for the sensing differential amplifier, by employing said output potentials of the two control circuits as virtual reference potentials for the pair of input transistors of the differential amplifier during a discriminating phase of the reading cycle. Two pass-transistors driven by a control signal provide to force to ground potential the output nodes of said control circuits, thus reestablishing a correct ground reference potential of the amplifier, during the final phase of amplification and storage of the extracted datum in an output latch, as well as during the successive standby period. Alternative embodiments also include various anti-overshoot circuits.
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公开(公告)号：ITVA910022D0
公开(公告)日：1991-07-31
申请号：ITVA910022
申请日：1991-07-31
Applicant: ST MICROELECTRONICS SRL , SGS THOMSON MICROELECTRONICS
Inventor： PASCUCCI LUIGI , OLIVO MARCO
IPC: G11C11/417 , G11C7/10 , G11C7/14 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/409 , G11C11/413
Abstract: Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by implifying the sensing process.
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公开(公告)号：DE69732637D1
公开(公告)日：2005-04-07
申请号：DE69732637
申请日：1997-12-22
Applicant: ST MICROELECTRONICS SRL
Inventor： CAPPELLETTI PAOLO , MAURELLI ALFONSO , OLIVO MARCO
Abstract: A method of self-test and correction of errors due to a loss charge for a flash memory constituted by an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided, implemented by realizing at least an additional row and at least an additional column of cells for each memory sector; storing parity codes is the additional row and column, and carrying out periodically a self-test routine and eventual correction routine composed of the following steps: repeating the sequential reading per bytes and parity check; verifying the consistency of the parity value with the value stored in the respective parity bit; if the verification is negative, retaining the current row address and proceeding to sequentially verify column parity starting from the first column until identifying the column for which the verification yields a negative result, and if the failed bit so individuated is "1" reprogramming it to "0".
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公开(公告)号：DE69428423D1
公开(公告)日：2001-10-31
申请号：DE69428423
申请日：1994-02-21
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA , PADOAN SILVIA , OLIVO MARCO
Abstract: A regulating circuit for discharging non-volatile memory cells (5) in an electrically programmable memory device, of the type which comprises: at least one switch connected between a programming voltage reference (VPP) and a line (SCR) shared by the source terminals of the transistors forming said memory cells (5), and at least one discharge connection between said common line (SCR) to the source terminals and a ground voltage reference (GND), further comprises a second connection to ground of the line (SCR) in which a current (Is) generator (G) is connected and a normally open switch (I1). Also provided is a logic circuit (3) connected to the line (SRC) to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch (I1) to make. This solution allows a slow discharging phase of the line (SRC) to be effected at the end of the erasing phase.
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公开(公告)号：DE69427277T2
公开(公告)日：2001-09-13
申请号：DE69427277
申请日：1994-01-31
Applicant: ST MICROELECTRONICS SRL
Inventor： OLIVO MARCO , MACCARRONE MARCO
Abstract: A new method for testing an electrically programmable non-volatile memory and comprising a cell matrix and a state machine which governs the succession and timing of the memory programming phases by means of some control signals (WEN, CEN, OEN and DU) provides exclusion of the internal state machine and modification of the meaning of at least one of the control signals (WEN, CEN, OEN and DU) to program directly the cell matrix and then verify programming correctness.
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Patent Agency Ranking
公开(公告)号：DE69427277D1
公开(公告)日：2001-06-28
申请号：DE69427277
申请日：1994-01-31
Applicant: ST MICROELECTRONICS SRL
Inventor： OLIVO MARCO , MACCARRONE MARCO
Abstract: A new method for testing an electrically programmable non-volatile memory and comprising a cell matrix and a state machine which governs the succession and timing of the memory programming phases by means of some control signals (WEN, CEN, OEN and DU) provides exclusion of the internal state machine and modification of the meaning of at least one of the control signals (WEN, CEN, OEN and DU) to program directly the cell matrix and then verify programming correctness.
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公开(公告)号：DE69421266T2
公开(公告)日：2000-05-18
申请号：DE69421266
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
Abstract: The circuit (1) comprises a section (2) generating a pulse signal (ATD) for asynchronously enabling the read phases; a section (4) generating precharge (PC) and detecting (DET) signals of adjustable duration, for controlling data reading from the memory (104) and data supply to the output buffers (106); a section (5) generating a noise suppressing signal (N) for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal (SP) in an out-like circuit (33); a section (6) generating a loading signal (L), the duration of which may be equal to that of the noise suppressing signal (N) or extended by an extension circuit (51) in the event the array presents slower elements which may thus be read; and a section (7) generating a circuit reset signal (END).
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公开(公告)号：DE69421266D1
公开(公告)日：1999-11-25
申请号：DE69421266
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , PADOAN SILVIA , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
Abstract: The circuit (1) comprises a section (2) generating a pulse signal (ATD) for asynchronously enabling the read phases; a section (4) generating precharge (PC) and detecting (DET) signals of adjustable duration, for controlling data reading from the memory (104) and data supply to the output buffers (106); a section (5) generating a noise suppressing signal (N) for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal (SP) in an out-like circuit (33); a section (6) generating a loading signal (L), the duration of which may be equal to that of the noise suppressing signal (N) or extended by an extension circuit (51) in the event the array presents slower elements which may thus be read; and a section (7) generating a circuit reset signal (END).
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公开(公告)号：DE69324694T2
公开(公告)日：1999-10-07
申请号：DE69324694
申请日：1993-12-15
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA MARIA , OLIVO MARCO
Abstract: A plurality of identical circuit blocks (PG0-PG15) is supplied with address signals (A0-A3,A0N-A3N) and each one generating a respective selection signal (P0-P15) which is activated by a particular logic configuration of said address signals (A0-A3,A0N-A3N) for the selection of a particular row (WL0-WL15) of the matrix; each one of said circuit blocks (PG0-PG15) also generates a carry-out signal (C00-C015) which is supplied to a carry-in input (CI0-CI15) of a following circuit block (PG0-PG15) and is activated when the respective selection signal (P0-P15) is activated; a first circuit block (PG0) of said plurality of circuit blocks (PG0-PG15) has the respective carry-in input (C10) connected to a reference voltage (GND); each of said circuit blocks (PG0-PG15) is also supplied with a control signal (E), which is activated by a control circuitry (6) of the memory device when, during a preprogramming operation preceding an electrical erasure of the memory device, a defective row (WL0-WL15) is addressed, to enable the activation of the respective selection signal (P0-P15) if the carry-out (C00-C014) signal supplying the respective carry-in input (CI1-CI15) is activated, so that two adjacent rows (WL0-WL15) can be simultaneously selected.
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公开(公告)号：DE69419723D1
公开(公告)日：1999-09-02
申请号：DE69419723
申请日：1994-02-18
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
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