公开(公告)号：US09901016B1

公开(公告)日：2018-02-20

申请号：US15488133

申请日：2017-04-14

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yung-Lin Chia

IPC: H05K9/00

CPC classification number: H05K9/0037 ,  H05K9/003

Abstract: An EMI shielding device is provided. A first shielding layer is formed on a first surface of a first substrate, and a first through hole is formed through the first substrate. A second substrate is mounted in an opening of the first through hole, and a second shielding layer is formed on a surface of the second substrate. A conductive paste is mounted between the first substrate and the at least one second substrate to electrically connected the first shielding layer and the second shielding layer. A protective layer, an antirust layer, and a shielding layer are sequentially mounted on the conductive paste. The EMI shielding device is mounted on a printed circuit board (PCB) by Surface Mount Technology. Therefore, the EMI shielding device may be firmly mounted on the PCB, and there is not any narrow gap that may leak electromagnetic radiation.

公开(公告)号：US09406641B2

公开(公告)日：2016-08-02

申请号：US13938335

申请日：2013-07-10

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yi-Fan Kao ,  Shuo-Hsun Chang ,  Yu-Te Lu ,  Kuo-Chun Huang

IPC: H01L23/00 ,  H01L23/31 ,  H05K3/46 ,  H01L23/498 ,  H05K1/02 ,  H05K1/18 ,  H01L25/10

CPC classification number: H01L24/81 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0271 ,  H05K1/183 ,  H05K3/4697 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/061 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate having a flip region with a through-opening and bonding to a Non-conductive Film to bond to a carrier board in order to form a compound carrier board structure. The baseplate is constructed with a low Thermal Expansion Coefficient material.

Abstract translation: Flip-Chip Chip-Scale封装的复合载体板结构及其制造方法提供了一种具有通孔的翻转区和与非导电膜结合以结合到载体板以形成化合物载体的底板 板结构。 底板由低热膨胀系数材料构成。

公开(公告)号：US09095084B2

公开(公告)日：2015-07-28

申请号：US13853303

申请日：2013-03-29

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yu-Te Lu ,  De-Hao Lu

IPC: H05K1/00 ,  H05K1/09 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H05K3/38

CPC classification number: H05K3/4647 ,  H05K1/0366 ,  H05K3/38

Abstract: A stacked multilayer structure, including a first circuit layer having bumps, a plastic film stacked on the first circuit layer to fill up the space among the bumps so as to form a co-plane, and a second circuit layer formed on the co-plane and connected to the first circuit layer. The plastic film includes a glass fiber layer which is embedded and not exposed.

Abstract translation: 一种堆叠多层结构，包括具有凸起的第一电路层，堆叠在第一电路层上以填充凸块之间的空间以形成共面的塑料膜，以及形成在共面上的第二电路层 并连接到第一电路层。 该塑料膜包括嵌入并不暴露的玻璃纤维层。

公开(公告)号：US20150044359A1

公开(公告)日：2015-02-12

申请号：US13960123

申请日：2013-08-06

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Hsueh-Ping Chien ,  Jun-Chung Hsu

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K3/4682 ,  H05K3/007 ,  H05K3/22 ,  H05K2201/2009 ,  H05K2203/0165 ,  H05K2203/0169 ,  H05K2203/162

Abstract: A method of manufacturing a thin support package structure includes the steps of: preparing a support plate formed with a plurality of grooves adjacent to an outer rim thereof, forming a releasing material layer on the support plate; forming a first circuit layer on the releasing material layer so as to form a thin circuit board; forming a dielectric layer on the releasing material layer; forming a plurality of openings in the dielectric layer; forming a second circuit layer on the dielectric layer; forming connection plugs by filling the openings; forming a solder mask on the dielectric layer; forming a plurality of notches on the lower surface of the support plate to communicate with the grooves, respectively; and removing the central part of the support plate between the notches and the central part of the releasing material on the support plate.

Abstract translation: 制造薄支撑包装结构的方法包括以下步骤：制备形成有与其外缘相邻的多个槽的支撑板，在支撑板上形成释放材料层; 在所述释放材料层上形成第一电路层以形成薄电路板; 在释放材料层上形成介电层; 在介电层中形成多个开口; 在所述电介质层上形成第二电路层; 通过填充开口形成连接插头; 在电介质层上形成焊料掩模; 在所述支撑板的下表面上分别形成多个凹槽以与所述凹槽连通; 并且将支撑板的中心部分移除在支撑板上的切口和释放材料的中心部分之间。

公开(公告)号：US20140295623A1

公开(公告)日：2014-10-02

申请号：US13853255

申请日：2013-03-29

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yu-Te Lu ,  De-Hao Lu

IPC: H01L21/56

CPC classification number: H01L21/4846 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/562 ,  H01L2221/68345 ,  H01L2224/73204

Abstract: Disclosed is a method of packaging a chip and a substrate, including the steps of forming a substrate with a thickness ranging from 70 to 150 μm, which comprises a dielectric layer, a circuit metal layer stacked on the dielectric layer and bonding pads higher than the dielectric layer by 10 to 15 μm; forming a stabilizing structure around the substrate to provide a receiving space; disposing the chip on the receiving space and bonding the pins of the chip with the bonding pads; and filling up the receiving space under the chip with a filling material to a total thickness ranging from 300 to 850 μm. Without the plastic molding process, the present invention reduces the cost and the total thickness, and further prevents the substrate from warping by use of the stabilizing fixing structure.

Abstract translation: 公开了一种封装芯片和基板的方法，包括以下步骤：形成厚度范围为70-150μm的基板，该基板包括介电层，堆叠在电介质层上的电路金属层和高于 介电层10〜15μm; 在所述基板周围形成稳定结构以提供接收空间; 将芯片放置在接收空间上，并将芯片的引脚与焊盘接合; 并用填充材料填充芯片下方的接收空间，总厚度为300至850μm。 没有塑料成型工艺，本发明降低了成本和总厚度，并且通过使用稳定固定结构进一步防止了基板翘曲。

公开(公告)号：US08754328B2

公开(公告)日：2014-06-17

申请号：US13663141

申请日：2012-10-29

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

IPC: H02G15/00 ,  H05K1/11

CPC classification number: H05K3/28 ,  H05K3/243 ,  H05K3/4644 ,  H05K2201/0347

Abstract: A laminate circuit board with a multi-layer circuit structure which includes a substrate, a first circuit metal layer, a second circuit metal layer, a first nanometer plating layer, a second nanometer plating layer and a cover layer is disclosed. The first circuit metal layer is embedded in the substrate or formed on at least one surface of the substrate which is smooth. The first nanometer plating layer with a smooth surface covers the first circuit metal layer. The second nanometer plating layer is formed on the other surface of the substrate and fills up the opening in the cover layer to electrically connect the first circuit metal layer. The junction adhesion is improved by the chemical bonding between the nanometer plating layer and the cover layer/the substrate. Therefore, the circuit metal layer does not need to be roughened and the density of the circuit increases.

Abstract translation: 公开了一种具有多层电路结构的叠层电路板，其包括基板，第一电路金属层，第二电路金属层，第一纳米镀层，第二纳米镀层和覆盖层。 第一电路金属层嵌入衬底中或形成在衬底的平滑的至少一个表面上。 具有光滑表面的第一纳米镀层覆盖第一电路金属层。 第二纳米镀层形成在基板的另一个表面上，并填满覆盖层中的开口以电连接第一电路金属层。 通过纳米电镀层和覆盖层/基板之间的化学键合来改善连接粘附。 因此，电路金属层不需要粗糙化，电路密度增加。

公开(公告)号：US08377815B2

公开(公告)日：2013-02-19

申请号：US13043463

申请日：2011-03-09

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

IPC: H01L21/44

CPC classification number: H01L24/13 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/00

Abstract: A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pad is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced.

Abstract translation: 公开了一种半导体负载板的制造方法。 该制造方法包括第一导电层形成步骤，第一图案化步骤，介电层形成步骤，钻孔步骤，第二导电层形成步骤，第二图案化步骤或两次图案化步骤，以及焊料连接步骤 。 在第二图案化步骤或二次图案化步骤中，在电介质层的开口中形成焊料焊盘，其中每个焊盘的高度高于电介质的高度，并且每个焊盘的宽度相等 达到或小于开口的最大宽度，使得在相同的区域中设置更宽的间隔，并且可以减少短路故障和电气干扰的问题。

公开(公告)号：US08315063B2

公开(公告)日：2012-11-20

申请号：US12547495

申请日：2009-08-26

Applicant: Jun-Chung Hsu

Inventor： Jun-Chung Hsu

IPC: H05K7/00

CPC classification number: H05K1/111 ,  H01L2224/05557 ,  H05K3/062 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2203/1184 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49156

Abstract: A solder pad structure with a high bondability to a solder ball is provided. The present invention provides a larger contact area with the solder ball so as to increase the bondability according to the principle that the bondability is positive proportional with the contact area therebetween. The solder pad structure includes a circuit board having a solder pad opening defined by a solder resist layer surrounding a circuit layer. The circuit layer within the solder pad opening is defined as a solder pad. In such a way, after filling the solder ball into the solder pad opening, besides walls of the solder pad opening, there is an extra contact area provided by a geometric shape of the solder pad for further improving the bondability of the solder pad and the solder ball.

Abstract translation: 提供了与焊球具有高粘合性的焊盘结构。 本发明提供了一种与焊球相比较大的接触面积，以便根据粘合性与它们之间的接触面积成正比的原理提高粘接性。 焊盘结构包括具有由围绕电路层的阻焊层限定的焊盘开口的电路板。 焊盘开口内的电路层被定义为焊盘。 以这种方式，在将焊球填充到焊盘开口中之后，除了焊盘开口的壁之外，还存在由焊料焊盘的几何形状提供的额外的接触面积，用于进一步提高焊盘的焊接性和 焊球

公开(公告)号：US08312624B1

公开(公告)日：2012-11-20

申请号：US13304340

申请日：2011-11-24

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  De-Hao Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  De-Hao Lu

IPC: H05K3/02

CPC classification number: H05K3/427 ,  H05K1/0206 ,  H05K3/421 ,  H05K2203/025 ,  H05K2203/0733 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for manufacturing a heat dissipation structure of a printed circuit board includes: forming a barrier layer on the dimple in the first copper plating layer; forming a nickel plating layer; removing the nickel plating layer and the barrier layer on the dimple; forming a second copper plating layer to make the total height of the first copper plating layer and the second copper plating layer in the second opening higher than that of the first copper plating layer in the first opening; filling the dimple in the second copper plating layer with an etching-resistant material; removing the second copper plating layer; removing the nickel plating layer and the etching-resistant material to make the second copper plating layer in the second opening being at the same height as the first copper plating layer in the first opening; and forming the heat dissipation structure by photolithography.

Abstract translation: 制造印刷电路板的散热结构的方法包括：在第一镀铜层的凹坑上形成阻挡层; 形成镀镍层; 去除凹坑上的镀镍层和阻挡层; 形成第二镀铜层，使第二开口中的第一镀铜层和第二镀铜层的总高度高于第一开口中的第一镀铜层的总高度; 用耐腐蚀材料填充第二镀铜层中的凹坑; 去除所述第二镀铜层; 去除镀镍层和耐腐蚀材料，使得第二开口中的第二镀铜层处于与第一开口中的第一铜镀层相同的高度; 并通过光刻法形成散热结构。

公开(公告)号：US08186054B2

公开(公告)日：2012-05-29

申请号：US12725460

申请日：2010-03-17

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

IPC: H01K3/10

CPC classification number: H05K3/4602 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: Structure and method of making a board having plating though hole (PTH) core layer substrate and stacked multiple layers of blind vias. More stacking layers of blind vias than conventional methods can be achieved. The fabrication method of the board having high-density core layer includes the following: after the making of the PTH, the filling material filled inside the PTH of the core layer is partially removed until the PTH has reached an appropriate flattened depression using etching; then image transfer and pattern plating are performed to fill and to level the depression portion up to a desired thickness to form a copper pad (overplating) as the core layer substrate is forming a circuit layer; finally using electroless copper deposition and the pattern plating to make the product.

Abstract translation: 制造具有电镀通孔（PTH）芯层衬底和层叠多层盲孔的板的结构和方法。 可以实现比常规方法更多的盲孔堆叠层。 具有高密度芯层的板的制造方法包括以下：在制造PTH之后，填充在芯层的PTH内部的填充材料被部分地去除，直到PTH已经通过蚀刻达到适当的平坦凹陷; 然后进行图像转印和图案电镀，以在芯层基板正在形成电路层时填充并使凹陷部分达到所需厚度以形成铜焊盘（过镀层）; 最后使用无电镀铜和图案电镀制成产品。