公开(公告)号：EP1841297A1

公开(公告)日：2007-10-03

申请号：EP07005727.8

申请日：2007-03-20

Applicant: TDK Corporation

Inventor： Iwata, Masashi

IPC: H05K1/02 ,  H04B1/40 ,  H03H7/46

CPC classification number: H05K1/0243 ,  H03H7/463 ,  H03H9/725 ,  H03H2001/0085 ,  H04B1/0057 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/1003 ,  H05K2201/10083

Abstract: A high frequency module (1) incorporates a layered substrate (200). The layered substrate has a bottom surface (200a) and a top surface (200b). Terminals (Rx11) are disposed on the bottom surface. SAW filters (121) and inductors (81) are mounted on the top surface. The layered substrate incorporates: a first conductor layer (433) connecting the SAW filters to the inductors; a second conductor layer (451) connected to the terminals and disposed at a location closer to the bottom surface than the first conductor layer; and a plurality of parallel signal paths (701,702) each of which is formed using at least one through hole (h25,h26) provided inside the layered substrate and each of which connects the first and second conductor layers to each other.

Abstract translation: 高频模块（1）结合了分层基板（200）。 分层基板具有底面（200a）和顶面（200b）。 终端（Rx11）放置在底部表面上。 SAW滤波器（121）和电感器（81）安装在顶面上。 分层基板包括：将SAW滤波器连接到电感器的第一导体层（433） 第二导体层（451），连接到所述端子并设置在比所述第一导体层更靠近所述底表面的位置处; 以及多个平行信号路径（701,702），每个平行信号路径使用设置在层叠基板内的至少一个通孔（h25，h26）形成，并且每个平行信号路径将第一和第二导体层彼此连接。

公开(公告)号：WO2014128892A1

公开(公告)日：2014-08-28

申请号：PCT/JP2013/054386

申请日：2013-02-21

Applicant: 株式会社PFU

Inventor： 吉永　斉司

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/115 ,  H05K3/42 ,  H05K2201/09636 ,  H05K2203/0242

Abstract: 　スルーホール１５同士が短絡することなく、スルーホール１５同士の間隔を小さくすることのできるプリント基板１を実現するために、プリント基板１に、絶縁層５を貫通すると共に内面に導電内面層１６が形成される穴として形成され、絶縁層５の両面側に配設される導電層１０同士を導電内面層１６によって導通させるスルーホール１５と、隣り合うスルーホール１５同士の間の位置で絶縁層５を貫通すると共に、隣り合う双方のスルーホール１５に連通し、絶縁層５の厚さ方向に亘ってスルーホール１５同士を連通させる穴である連通穴２０と、を備える。

Abstract translation: 为了实现能够在不使通孔（15）短路的情况下减小通孔（15）之间的间隔的印刷电路板（1），印刷电路板（1）设置有：通孔（15） ），其形成为具有形成在其内表面上的导电内表面层（16）的孔的绝缘层（5），并且使用所述导电内表面层（16）引导导电层（16） 10）布置在绝缘层（5）的两个表面上; 以及在与相邻通孔（15）连接的相邻通孔（15）之间的位置处穿过绝缘层（5）的连接孔（20），并且是连接通孔 （15）沿着绝缘层（5）的厚度方向。

公开(公告)号：WO2008105478A1

公开(公告)日：2008-09-04

申请号：PCT/JP2008/053450

申请日：2008-02-27

Applicant: 京セラ株式会社 ,  前谷 麿明

Inventor： 前谷 麿明

IPC: H01P1/04 ,  H01P3/04 ,  H05K1/02

CPC classification number: H05K1/0245 ,  H01L2924/0002 ,  H05K1/0251 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09636 ,  H05K2201/09672 ,  H01L2924/00

Abstract: 　本発明は、配線基板、電気信号伝送システムおよび電子機器に関する。配線基板１０は、誘電体基板１１、第１線路導体１２ａ、第１ビア導体１４ａ、第２線路導体１２ｂ、および第２ビア導体１４ｂを備え、第１線路導体１２ａと第２線路導体１２ｂとは中間層１７ｂの上下面１８，１９上に沿って設けられる。第１ビア導体１４ａは、誘電体基板１１の一方の主面１１ａから第１線路導体１２ａの一端部まで設けられる。また第２ビア導体１４ｂは、誘電体基板１１の一方の主面１１ａから第２線路導体１２ｂの一端部まで設けられ、第１線路導体１２ａの電気長は、第２線路導体１２ｂの電気長より大きく設定される。

Abstract translation: 提供了布线板，电信号传输系统和电子设备。 布线板（10）设置有电介质基板（11），第一线路导体（12a），第一通孔导体（14a），第二线路导体（12b）和第二通路导体（14b）。 第一线路导体（12a）和第二线路导体（12b）沿着中间层（17b）的上表面和下表面（18,19）布置。 第一通孔导体（14a）从电介质基板（11）的一个主表面（11a）设置到第一线路导体（12a）的一个端部。 第二通路导体（14b）从电介质基板（11）的主表面（11a）布置到第二线路导体（12b）的一个端部。 第一线导体（12a）的电气长度被设定为比第二线路导体（12b）的长度长。

公开(公告)号：WO2008044974A1

公开(公告)日：2008-04-17

申请号：PCT/SE2006/050395

申请日：2006-10-11

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) ,  LIGANDER, Per

Inventor： LIGANDER, Per

IPC: H05K1/14

CPC classification number: H05K1/0263 ,  H05K1/181 ,  H05K2201/09636 ,  H05K2201/10272 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: The invention refers to a power distribution device (12) for a circuit board arrangement (2) comprising a number of electronic devices (IC1-IC7) and wherein the power distribution device (12) comprises a voltage layer (15). The invention is characterized in that the power distribution device (12) forms a separate unit attachable to at least a major part of the electronic devices (IC1-IC7) and that the extension of the power distribution device (12) is customized dependent on the positions of the electronic devices (IC1-IC7) so that the power distribution device (17) distributes power to the at least a major part of the electronic devices (IC1-IC7) when being attached to the electronic devices (IC1-IC7).

Abstract translation: 本发明涉及一种用于包括多个电子设备（IC1-IC7）的电路板装置（2）的配电装置（12），其中配电装置（12）包括电压层（15）。 本发明的特征在于，配电装置（12）形成可附接到电子装置（IC1-IC7）的至少主要部分的分离单元，并且配电装置（12）的延伸根据 电子设备（IC1-IC7）的位置，使得配电装置（17）在附接到电子设备（IC1-IC7）时将电力分配给至少大部分电子设备（IC1-IC7）。

公开(公告)号：EP2779810A3

公开(公告)日：2014-11-26

申请号：EP14158757.6

申请日：2014-03-11

Applicant: Tripod Technology Corporation

Inventor： Huang, Bo-Shiung ,  Yang, Wei-Hsiung ,  Shih, Han-Ching ,  Lin, Cheng-Feng

IPC: H05K1/16 ,  H05K3/46 ,  H01F17/06 ,  H05K1/11 ,  H05K1/02 ,  H05K3/42

CPC classification number: H05K1/0271 ,  H01F17/0033 ,  H01F17/062 ,  H01F27/2804 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/029 ,  H05K2201/086 ,  H05K2201/09636 ,  H05K2203/1178 ,  Y10T29/49165

Abstract: A printed circuit board package structure includes a substrate (110) having a first surface (111) and a second surface (113), a ring-shaped magnetic element (120), an adhesive layer (130), conductive portions (140) and conductive channels (150). The first and second surfaces respectively have first (114) and second (116) metal portions. A ring-shaped concave portion (112) is formed on a position not covered by the first metal portions of the first surface. The ring-shaped magnetic element is placed in the ring-shaped concave portion. The adhesive layer covers the first metal portions and the ring-shaped magnetic element. The conductive portions are formed on the adhesive layer. The conductive channels penetrate the conductive portions, the adhesive layer, and the substrate, and are respectively located in an inner wall (122) and outside an outer wall (124) of the ring-shaped concave portion. Each of the conductive channels includes a conductive film (152) electrically connects to the aligned conductive portion and second metal portion.

公开(公告)号：EP2154747A1

公开(公告)日：2010-02-17

申请号：EP09167215.4

申请日：2009-08-04

Applicant: SELEX COMMUNICATIONS S.p.A.

Inventor： Russo, Massimo ,  Di Maggio, Francesco ,  Pomona, Ignazio

IPC: H01P5/08 ,  H05K1/02

CPC classification number: H05K1/0251 ,  H01P1/047 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/09636

Abstract: Described herein is a device with vertical transition (1) having a plurality of layers set on top of one another, which define a first transmission line (2) and a second transmission line (3); the first transmission line (2) has a first conductive path (5) and the second transmission line (3) has a second conductive path (10); an electrical connection structure (20, 21) extends vertically through one or more of the layers set on top of one another and provides the connection between the first conductive path (5) and the second conductive path (10). The electrical connection structure (20, 21) generates a condition of resonance for a signal travelling in the first conductive path (5) and/or second conductive path (10) and having a frequency selected in a band of pre-set frequencies.

Abstract translation: 这里描述的是具有垂直转换（1）的装置，其具有设置在彼此之上的多个层，其限定第一传输线（2）和第二传输线（3）; 第一传输线（2）具有第一导电路径（5），第二传输线（3）具有第二导电路径（10）; 电连接结构（20,21）垂直延伸穿过设置在彼此之上的一层或多层，并提供第一导电路径（5）和第二导电路径（10）之间的连接。 电连接结构（20,21）产生在第一导电路径（5）和/或第二导电路径（10）中行进并且具有在预定频率的频带中选择的频率的信号的谐振条件。

公开(公告)号：EP1956615A3

公开(公告)日：2008-12-24

申请号：EP07254736.7

申请日：2007-12-07

Applicant: Renesas Technology Corp.

Inventor： Takahashi, Wataru ,  Tsuchida, Shigeru ,  Okabe, Hiroshi

IPC: H01F17/00 ,  H05K1/02 ,  H05K1/16 ,  H04B1/38 ,  H01L23/48 ,  H01L23/52 ,  H01L23/64

CPC classification number: H05K1/165 ,  H01F17/0006 ,  H01L2924/0002 ,  H03H7/0115 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/383 ,  H03H7/465 ,  H03H2001/0085 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/16 ,  H05K3/429 ,  H05K2201/09636 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A parallel resonant circuit is realized by stacking first to fourth wiring patterns (MS21,MS22,MS23,MS24) each having at least an inductance element. One of the adjacent first and second wiring patterns is set to a signal input node (Nin) and the other thereof is set to a signal output node (Nout). Then, the signal input node is connected to the signal output node via inductance elements of the first wiring pattern, third wiring pattern, fourth wiring pattern and second wiring pattern in order. By adjacently forming wiring layers of the signal input and output nodes, a capacitance value between the input and output nodes is increased compared to that when they are separated. Also, by increasing the line width of the first and second wiring patterns, the capacitance value can be further increased. Therefore, it is possible to achieve a large capacitance value in a small area and downsizing of the electronic device.

公开(公告)号：EP1269808A1

公开(公告)日：2003-01-02

申请号：EP01916828.5

申请日：2001-03-30

Applicant: DYCONEX PATENTE AG

Inventor： SCHMIDT, Walter

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/0263 ,  H05K1/0268 ,  H05K1/0272 ,  H05K1/0274 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K1/144 ,  H05K1/162 ,  H05K1/185 ,  H05K3/005 ,  H05K3/0055 ,  H05K3/0061 ,  H05K3/041 ,  H05K3/046 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4084 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2201/10598 ,  H05K2203/0108 ,  H05K2203/0195 ,  H05K2203/0285 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00

Abstract: According to the invention, a microperforation (PMP) process step is combined with the lamination process. To this end, a dielectric layer (11,11') and a prefabricated product (1) are placed between two perforation dies (21,23) or a support and a perforation die. The prefabricated product (1) is partially covered by a conducting layer forming structures to be contacted by microvias. Pressure is applied on the perforation die (21,22), perforation tips of the perforation dies forming microvias for contacting the structures. A surface of the dielectric layer (11,11') or the prefabricated product (1) is configurated or coated to in a manner that the prefabricated product (1) and the dielectric layer (11,11') stick to each other after the pressure has been applied.

公开(公告)号：KR1020150021342A

公开(公告)日：2015-03-02

申请号：KR1020130098593

申请日：2013-08-20

Applicant: 삼성전기주식회사

Inventor： 김정근

IPC: H05K3/46

CPC classification number: H05K1/0265 ,  H05K1/115 ,  H05K2201/09536 ,  H05K2201/09636 ,  H05K2201/09836 ,  H05K2201/09854

Abstract: 본 발명은 다층인쇄회로기판에 관한 것이다.
본 발명에 따른 다층인쇄회로기판은, 다수의 회로층, 다수의 회로층 사이에 각각 형성된 절연층 및 절연층과 회로층을 관통하고, 다수의 회로층을 전기적으로 접속하는 비아를 포함한다. 또한, 비아는 제1 비아 및 제2 비아를 포함하며, 제2 비아는 제1 비아의 직경보다 큰 대직경 비아이다.

Abstract translation: 本发明涉及一种多层印刷电路板。 根据本发明的多层印刷电路板包括多个电路层，形成在多个电路层之间的绝缘层和穿过绝缘层和多个电路层并且与多个电路电连接的通孔 电路层。 此外，通孔包括第一通孔和第二通孔。 第二通孔的直径大于第一通孔的直径。

公开(公告)号：EP2939507A1

公开(公告)日：2015-11-04

申请号：EP13866930.4

申请日：2013-12-12

Applicant: FCI Asia Pte. Ltd.

Inventor： RENGARAJAN, Madhumitha ,  DE GEEST, Jan ,  SMITH, Stephen B. ,  SERCU, Stefaan H.

IPC: H05K3/40

CPC classification number: H05K1/116 ,  H05K1/0222 ,  H05K1/0251 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2203/0207 ,  H05K2203/0242

Abstract: In accordance with the various embodiments disclosed herein, an improved electrical connector footprint, such as on printed circuit boards (PCB), is described. For example, antipads can have a variety of sizes and pairs of differential signal traces can define centerlines that are spaced apart from each other.