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    72.
    发明专利
    未知

    公开(公告)号：DE10344862A1

    公开(公告)日：2004-04-15

    申请号：DE10344862

    申请日：2003-09-26

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

    IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

    73.
    发明专利
    未知

    公开(公告)号：DE10310571A1

    公开(公告)日：2003-10-02

    申请号：DE10310571

    申请日：2003-03-11

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  MCSTAV KEVIN

    IPC: H01L21/8242 ,  H01L29/10 ,  H01L29/78 ,  H01L27/108

    Abstract: Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold implant moved from the conventional location of midway between source and drain to a point no more than one third of the channel length below the bottom of the source.

    74.
    发明专利
    未知

    公开(公告)号：DE10215666A1

    公开(公告)日：2002-11-07

    申请号：DE10215666

    申请日：2002-04-09

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： DYER THOMAS ,  MALIK RAIEEV ,  DIVAKARUNI RAMA ,  MANDELMAN JACK A ,  JAIPRAKASH V C

    IPC: H01L21/316 ,  H01L21/318 ,  H01L21/8242

    Abstract: A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.

    78.
    发明专利
    未知

    公开(公告)号：DE69934357D1

    公开(公告)日：2007-01-25

    申请号：DE69934357

    申请日：1999-06-17

    Applicant: SIEMENS AG ,  IBM

    Inventor： GAMBINO JEFFREY P ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.

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