公开(公告)号：DE10310161A1

公开(公告)日：2004-09-23

申请号：DE10310161

申请日：2003-03-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER

IPC: B81B3/00 ,  H01L21/822 ,  H01L27/04 ,  H02K35/02 ,  B81B7/02 ,  H02M1/00

Abstract: A monolithic integrated circuit (100) comprises a functional unit on a substrate (101) with a coupled energy supply unit comprising an inductance (103) and a permanent magnet (102) which moves with respect to the inductance on vibration to generate an electrical supply for the functional unit, which is preferably a sensor.

公开(公告)号：DE59709521D1

公开(公告)日：2003-04-17

申请号：DE59709521

申请日：1997-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  HARTNER WALTER ,  MAZURE-ESPEJO CARLOS

IPC: H01L21/8242 ,  H01L27/108

Abstract: A method for producing a memory configuration that comprises a multiplicity of memory cells, and has storage capacitors whose first electrodes are configured in plate form in a parallel manner one above the other. These electrodes are in electrical contact with selection transistors of the memory cell through contact plugs having different lengths. The first electrodes preferably extend beyond the cell area of one memory cell.

公开(公告)号：DE19957122C2

公开(公告)日：2002-08-29

申请号：DE19957122

申请日：1999-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  HARTNER WALTER

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/314 ,  H01L27/115 ,  H01L27/11502 ,  H01G7/06 ,  H01G4/008 ,  H01L21/8239

公开(公告)号：DE10058965A1

公开(公告)日：2002-06-13

申请号：DE10058965

申请日：2000-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  KROENKE MATTHIAS

IPC: G11C7/20 ,  G11C11/404 ,  G11C11/4063

Abstract: The RAM memory has a number of memory cells whose logical state can be varied by a control voltage. At least some memory cells include an additional device that can be activated by a forced control voltage that is different from the control voltage in order to impose a defined logical state on the memory cells.

公开(公告)号：DE10039411A1

公开(公告)日：2002-02-28

申请号：DE10039411

申请日：2000-08-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HINTERMAIER FRANK ,  WEINRICH VOLKER ,  HARTNER WALTER ,  SCHINDLER GUENTHER ,  ENGELHARDT MANFRED

IPC: H01L21/02 ,  H01L21/311

Abstract: The invention relates to methods for structuring ferroelectric layers on semiconductor substrates. The inventive methods retain or regenerate the adherence and breakdown voltage resistance of the ferroelectric layer, which is especially significant for producing storage capacitors in large-scale integrated FeRAM and DRAM memory components.

公开(公告)号：DE59705912D1

公开(公告)日：2002-01-31

申请号：DE59705912

申请日：1997-09-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  HARTNER WALTER ,  HINTERMAIER FRANK ,  MAZURE-ESPEJO CARLOS

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11517

Abstract: A method for producing an integrated semiconductor memory configuration, in particular uses ferroelectric materials as storage dielectrics. A conductive connection between a first electrode of a storage capacitor and a selection transistor is produced only after deposition of the storage dielectric.

公开(公告)号：DE10010288C1

公开(公告)日：2001-09-20

申请号：DE10010288

申请日：2000-02-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINRICH VOLKER ,  KASKO IGOR ,  HARTNER WALTER ,  SCHINDLER GUENTHER

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/8246 ,  H01L21/8239

Abstract: The manufacturing method has a ferroelectric layer (13) of varying thickness applied to an electrode structure (11) which has at least 2 different height levels, before application of a second electrode structure (12) to the ferroelectric layer. The different height levels are formed in the first electrode structure by formed etched edges, or by providing a step in a barrier layer (14) before deposition of the electrode structure, with a centrifugal coating process used for deposition of the ferroelectric layer.

公开(公告)号：DE19926767A1

公开(公告)日：2000-12-21

申请号：DE19926767

申请日：1999-06-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER THOMAS ,  SCHINDLER GUENTHER

IPC: H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: Two source/drain regions (12, 22, 32) between which a channel region is arranged are provided for in a semiconductor substrate (11, 21, 31). A gate dielectric comprising a dielectric intermediate layer (13, 23, 33) and a dielectric structure (14, 24, 34) is positioned on the surface of the channel region. The dielectric structure (14, 24, 34) borders on the dielectric intermediate layer (12, 22, 32) on at least one side which is directed towards one of the source/drain regions (12, 22, 32), whereby the thickness of the gate dielectric above the edge of the source/drain region is greater than the thickness of the dielectric intermediate layer.

公开(公告)号：DE19926766A1

公开(公告)日：2000-12-21

申请号：DE19926766

申请日：1999-06-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER THOMAS ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG ,  ROEHR THOMAS ,  SCHINDLER GUENTHER ,  HARTNER WALTER ,  BOEHM THOMAS ,  WENDT HERMANN

IPC: H01L29/78

Abstract: According to the invention, two source/drain regions (121, 122) between which a channel region is arranged are provided for on a semiconductor substrate. On the surface of the channel region a gate dielectric (13) is positioned. Above the gate dielectric (13) a ferroelectric layer (14) and a gate electrode (15) are arranged. The ferroelectric layer (14) overlaps one of the source/drain regions (121). To change the polarization of the ferroelectric layer (14) a voltage can be applied between the gate electrode (15) and the overlapped source/drain region (121).