公开(公告)号：EP1841298A3

公开(公告)日：2008-05-07

申请号：EP07110136.4

申请日：2005-02-14

Applicant: MOLEX INCORPORATED

Inventor： Regnier, Kent, E. ,  Brunker, David, L. ,  Ogbuokiri, Martin, U.

IPC: H05K1/11 ,  H05K1/02 ,  H01L23/64 ,  H01L23/66 ,  H01R24/00 ,  H01R12/16

CPC classification number: H05K1/0251 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10189 ,  H01L2924/00

Abstract: A circuit board (600) design is disclosed that is useful in high speed differential signal applications uses a circuit trace exit structure (620) and optionally a via arrangement. The circuit trace exit structure involves the exit portions (620) of the circuit traces (550) of the differential signal vias (609) to follow a path where the traces then meet with and join to the transmission line portions (552,612) of the conductive traces (550). In the via arrangement, sets of differential signal pair vias (551,609) and an associated ground (593a) are arranged adjacent to each other in a repeating pattern. The differential signal vias of each pair (591) are spaced closer to their associated ground via (593a) than the spacing between the adjacent differential signal pair associated ground (593b) so that differential signal vias exhibit a preference for electrically coupling to their associated ground vias.

Abstract translation: 公开了一种在高速差分信号应用中使用电路走线出口结构（620）和可选的通孔装置的电路板（600）设计。 电路走线出口结构涉及差分信号通孔（609）的电路迹线（550）的出口部分（620），以跟随路径，其中迹线然后与导体的传输线部分（552,612）相接并连接 痕迹（550）。 在通孔布置中，差分信号对通孔（551,609）和相关联的接地（593a）的组以重复图案彼此相邻布置。 每对（591）的差分信号通孔（593a）比相邻的差分信号对相关联的接地（593b）之间的间隔更靠近其相关联的接地，使得差分信号通孔表现出对它们的相关接地电耦合的偏好 孔。

公开(公告)号：EP1855517A1

公开(公告)日：2007-11-14

申请号：EP07008977.6

申请日：2007-05-03

Applicant: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO

Inventor： Suzuki, Norihito ,  Minoura, Akihiro

IPC: H05K3/34

CPC classification number: H05K3/3447 ,  H05K1/0201 ,  H05K1/116 ,  H05K3/3468 ,  H05K2201/09572 ,  H05K2201/09636 ,  H05K2201/09781 ,  H05K2203/045

Abstract: In the vicinity of soldering through holes of lands for soldering a lead terminal in a multilayer printed board, electrically isolated lands are provided to form a thermal through hole. In the soldering, by the radiation and supply of heat of a lead-free solder filled in the thermal through hole, it is possible to suppress the radiation of heat of the soldering through hole. Thus, it is possible to achieve a sufficient solder rise and to obtain an excellent soldering property.

Abstract translation: 在用于焊接多层印刷电路板中的引线端子的焊盘通孔附近，设置电隔离焊盘以形成热通孔。 在焊接中，通过填充在热通孔中的无铅焊料的放射和供热，可以抑制焊接通孔的热辐射。 因此，可以实现足够的焊料上升并获得优异的焊接性能。

公开(公告)号：EP1841298A2

公开(公告)日：2007-10-03

申请号：EP07110136.4

申请日：2005-02-14

Applicant: MOLEX INCORPORATED

Inventor： Regnier, Kent, E. ,  Brunker, David, L. ,  Ogbuokiri, Martin, U.

IPC: H05K1/11 ,  H05K1/02 ,  H01L23/64 ,  H01L23/66 ,  H01R24/00 ,  H01R12/16

CPC classification number: H05K1/0251 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10189 ,  H01L2924/00

Abstract: A circuit board (600) design is disclosed that is useful in high speed differential signal applications uses a circuit trace exit structure (620) and optionally a via arrangement. The circuit trace exit structure involves the exit portions (620) of the circuit traces (550) of the differential signal vias (609) to follow a path where the traces then meet with and join to the transmission line portions (552,612) of the conductive traces (550). In the via arrangement, sets of differential signal pair vias (551,609) and an associated ground (593a) are arranged adjacent to each other in a repeating pattern. The differential signal vias of each pair (591) are spaced closer to their associated ground via (593a) than the spacing between the adjacent differential signal pair associated ground (593b) so that differential signal vias exhibit a preference for electrically coupling to their associated ground vias.

公开(公告)号：EP1269808B1

公开(公告)日：2007-08-22

申请号：EP01916828.5

申请日：2001-03-30

Applicant: Dyconex AG

Inventor： SCHMIDT, Walter

IPC: H05K3/40 ,  H05K3/46

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/0263 ,  H05K1/0268 ,  H05K1/0272 ,  H05K1/0274 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K1/144 ,  H05K1/162 ,  H05K1/185 ,  H05K3/005 ,  H05K3/0055 ,  H05K3/0061 ,  H05K3/041 ,  H05K3/046 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4084 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2201/10598 ,  H05K2203/0108 ,  H05K2203/0195 ,  H05K2203/0285 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00

Abstract: According to the invention, a microperforation (PMP) process step is combined with the lamination process. To this end, a dielectric layer (11,11') and a prefabricated product (1) are placed between two perforation dies (21,23) or a support and a perforation die. The prefabricated product (1) is partially covered by a conducting layer forming structures to be contacted by microvias. Pressure is applied on the perforation die (21,22), perforation tips of the perforation dies forming microvias for contacting the structures. A surface of the dielectric layer (11,11') or the prefabricated product (1) is configurated or coated to in a manner that the prefabricated product (1) and the dielectric layer (11,11') stick to each other after the pressure has been applied.

公开(公告)号：EP1269804A1

公开(公告)日：2003-01-02

申请号：EP01913463.4

申请日：2001-03-29

Applicant: DYCONEX PATENTE AG

Inventor： SCHMIDT, Walter

IPC: H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0263 ,  H05K1/0268 ,  H05K1/0272 ,  H05K1/0274 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K1/144 ,  H05K1/162 ,  H05K1/185 ,  H05K3/005 ,  H05K3/0055 ,  H05K3/0061 ,  H05K3/041 ,  H05K3/046 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4084 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2201/10598 ,  H05K2203/0108 ,  H05K2203/0195 ,  H05K2203/0285 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/163 ,  Y02P70/613 ,  H01L2924/00

Abstract: The electrical connecting element comprises an essentially stiff core, essentially mechanically stiff and PCI/HDIs with conductor paths serving as interconnect, wherein the core comprises two parts (1, 3) which can be fixed to each other. Between the two parts, a cavity (101) can be formed, in which components (103) producing a lot of heat or requiring protection from environmental influences can be placed.

公开(公告)号：KR1020070115785A

公开(公告)日：2007-12-06

申请号：KR1020070053904

申请日：2007-06-01

Applicant: 후지쯔 가부시끼가이샤

Inventor： 사이토우아키요시 ,  미도리카와다케시 ,  구라이시도루 ,  구마가이지카유키 ,  후지모토마사시 ,  아베겐이치로

IPC: H05K3/46

CPC classification number: H05K1/0224 ,  H01L2924/0002 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4661 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/0959 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2203/0425 ,  H05K2203/063 ,  Y10T29/49117 ,  H01L2924/00

Abstract: A buildup board, and an electronic component and an apparatus including the same are provided to improve a transmission characteristic simply with respect to a conventional method. A buildup board includes a plurality of buildup layers(150a,150b) stacked on both sides of a core layer(140). At least one of the core layer and the buildup layers has a multi-layered structure. The multi-layered structure includes a signal wiring pattern, a pad(152b) connected to the signal wiring pattern, an insulation part(156) arranged around the pad at the same layers as the pad, and a conductor(154) arranged around the insulation unit at the same layers. A keep out is different from at least two place of the multi-layered structure, wherein the keep out is defined by a minimum interval between a contour of the pad among the same layers and the conductor nearest to the pad.

Abstract translation: 提供了一种积木板，以及一种电子元器件和一种包括该构成板的装置，以简单地提供传统的方法。 积层板包括堆叠在芯层（140）两侧的多个堆积层（150a，150b）。 核心层和堆积层中的至少一个具有多层结构。 多层结构包括信号布线图案，连接到信号布线图案的焊盘（152b），与焊盘相同层布置在焊盘周围的绝缘部分（156），以及围绕 绝缘单元在同一层。 保护区与多层结构的至少两个位置不同，其中保留区由相同层中的垫的轮廓和最靠近垫的导体之间的最小间隔限定。

公开(公告)号：KR1020070015210A

公开(公告)日：2007-02-01

申请号：KR1020067024755

申请日：2005-05-16

Applicant: 씨-코어 테크놀로지즈, 인코포레이티드

Inventor： 바소야칼루케이.

IPC: H05K1/16

CPC classification number: H05K3/4641 ,  H05K1/115 ,  H05K3/0005 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4638 ,  H05K2201/0281 ,  H05K2201/0323 ,  H05K2201/068 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Printed wiring boards and methods of manufacturing printed wiring boards are disclosed. In one aspect of the invention, the printed wiring boards include electrically conductive constraining cores having at least one resin filled channel. The resin filled channels perform a variety of functions that can be associated with electrical isolation and increased manufacturing yields. ® KIPO & WIPO 2007

Abstract translation: 公开了印刷电路板和制造印刷电路板的方法。 在本发明的一个方面，印刷电路板包括具有至少一个树脂填充通道的导电约束芯。 填充树脂的通道执行各种功能，可以与电气隔离和增加的制造产量相关联。 ®KIPO＆WIPO 2007

公开(公告)号：WO2009144829A1

公开(公告)日：2009-12-03

申请号：PCT/JP2008/060090

申请日：2008-05-26

Applicant: NEC CORPORATION ,  KUSHTA, Taras ,  SAKAI, Jun ,  KOUTA, Hikaru

Inventor： KUSHTA, Taras ,  SAKAI, Jun ,  KOUTA, Hikaru

IPC: H05K3/46

CPC classification number: H05K1/0245 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: A multilayer substrate is provided with a conductor plane region in which a plurality of conductor planes are disposed; a clearance region disposed adjacent to the conductor plane region so that the plurality of conductor planes are excluded from the clearance region. A plurality of signal vias are disposed through the clearance region so that the plurality of signal vias are isolated from the plurality of conductor planes. A conductor post is connected to one of the plurality of conductor planes and disposed between two of the signal vias in the clearance region.

Abstract translation: 多层基板设置有布置有多个导体平面的导体平面区域; 与所述导体平面区域相邻设置的间隙区域，以使所述多个导体平面从所述间隙区域排除。 多个信号通孔设置穿过间隙区域，使得多个信号通孔与多个导体平面隔离。 导体柱连接到多个导体平面中的一个并且设置在间隙区域中的两个信号通孔之间。

公开(公告)号：WO2009028108A1

公开(公告)日：2009-03-05

申请号：PCT/JP2007/067456

申请日：2007-08-31

Applicant: NEC CORPORATION ,  KUSHTA, Taras

Inventor： KUSHTA, Taras

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K1/0251 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09454 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09781

Abstract: A multi-layer substrate includes a planar transmission line structure and a signal via, which are connected by a multi-tier transition. The multi-tier transition includes a signal via pad configured to serve for a full-value connection of the signal via and the planar transmission line; and a dummy pad connected to the signal via, formed in an area of a clearance hole in a conductor layer disposed between a signal terminal of the signal via and the planar transmission line, and isolated from the conductor layer.

Abstract translation: 多层基板包括通过多层转换连接的平面传输线结构和信号通孔。 多层转换包括经配置以用于信号通孔和平面传输线的全值连接的信号通孔; 以及连接到信号通孔的虚拟焊盘，形成在布置在信号通孔的信号端子和平面传输线之间并与导体层隔离的导体层中的间隙孔的区域中。

公开(公告)号：WO2007102597A1

公开(公告)日：2007-09-13

申请号：PCT/JP2007/054621

申请日：2007-03-02

Applicant: NEC CORPORATION ,  NEC Electronics Corporation ,  KUSHTA, Taras ,  NARITA, Kaoru ,  KANEKO, Tomoyuki ,  OGOU, Shin-ichi

Inventor： KUSHTA, Taras ,  NARITA, Kaoru ,  KANEKO, Tomoyuki ,  OGOU, Shin-ichi

IPC: H05K3/46

CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09381 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09727

Abstract: According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; The length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.

Abstract translation: 根据一个实施例，形成在多层基板中连接通孔结构和平面传输线的宽带转变，作为信号通孔焊盘和布置在相同导体层处的平面传输线之间的中间连接。 过渡的横向尺寸等于一端的通孔焊盘直径和另一端的带宽度; 转换的长度可以等于平面传输线方向上的间隙孔的特征尺寸，或者定义为根据通过三维全波模拟获得的数值图在时域中提供最小的额外的电抗 。