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公开(公告)号：KR100538996B1
公开(公告)日：2005-12-27
申请号：KR1020030039661
申请日：2003-06-19
Applicant: 한국전자통신연구원
IPC: H01L31/09
Abstract: 본 발명은 멤스(MEMS) 공정을 적용한 초전형 적외선 센서에 관한 것으로, 적외선 센서 구조체의 최상부에 위치하는 적외선 흡수층을 실리콘 산화막(SiO
2 )으로 형성하여 약 8 내지 12㎜ 대역의 적외선 파장에 대하여 뛰어난 흡수 효과를 보이고, 센서 픽셀(pixel)의 보호막 역할을 할 수 있게 한다. 또한, 적외선 흡수층, 지지아암 및 기둥을 일체형으로 형성하여 센서 구조체의 구조를 견고하게 하고, 제작 공정의 단계를 획기적으로 감소시켜 공정 수율을 높인다.-
公开(公告)号：KR1020050066932A
公开(公告)日：2005-06-30
申请号：KR1020040015070
申请日：2004-03-05
Applicant: 한국전자통신연구원
IPC: H01L29/78
CPC classification number: H01L29/78696 , H01L21/0415 , H01L21/28255
Abstract: 본 발명은 균일 두께를 가진 스트레인드 실리콘 채널이 형성가능한 반도체 소자용 기판 제조방법 및 이를 이용한 반도체 소자의 제조방법에 관한 것으로, 본 발명의 반도체 소자용 기판 제조방법은 제 1 실리콘 기판 상에 도핑된 SiGe층 및 스트레인드 실리콘 채널층을 에피텍셜 공정으로 차례로 성장하는 단계와, 수소 또는 질소 이온을 상기 제 1 실리콘 기판의 일영역에 주입하여 이온 주입층이 상기 제 1 실리콘 기판을 2개의 영역으로 양분하도록 하는 단계와, 제 1 산화막이 형성된 제 2 실리콘 기판을 상기 제 1 실리콘 기판의 상기 스트레인드 실리콘 채널층이 형성된 면과 대향하도록 서로 부착하는 단계와, 제 1 실리콘 기판과 제 2 실리콘 기판을 이온 주입층을 기준으로 분리하는 단계를 포함한다.
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公开(公告)号：KR1020050064564A
公开(公告)日：2005-06-29
申请号：KR1020030096035
申请日：2003-12-24
Applicant: 한국전자통신연구원
IPC: G09G3/30
CPC classification number: G09G3/30 , G09G2310/027 , G09G2320/0276
Abstract: 본 발명은 디지털 신호를 아날로그 신호로 변환하고 이 변환과정에서 동시에 램프 신호를 생성하는 디지털-아날로그 변환/램프 회로를 구비하는 능동 구동형 EL의 소스 구동회로를 제공한다. 이를 통해 온도나 문턱전압 변동에 무관하고 종래의 램프 회로를 사용하지 않을 수 있어 고집적도가 가능하도록 할 수 있다.
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公开(公告)号：KR100491978B1
公开(公告)日：2005-05-27
申请号：KR1020030023213
申请日：2003-04-12
Applicant: 한국전자통신연구원
IPC: H01L27/10
CPC classification number: H01L45/06 , H01L45/1226 , H01L45/126 , H01L45/144 , H01L45/1683 , H01L45/1691
Abstract: 저 전력 동작이 가능한 상 변화 메모리 소자 및 그 제조 방법을 제공한다. 본 발명의 일 관점에 따른 상변화 메모리 소자는 가열층으로 사용되는 제1전극과, 제1전극과 측방향으로 대향되는 제2전극, 및 제1전극과 제2전극의 사이에 도입되고 적어도 제1전극의 측면에 접촉하는 상변화 물질로 이루어진 메모리층을 포함하여 구성된다.
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公开(公告)号：KR100461506B1
公开(公告)日：2004-12-14
申请号：KR1020020012670
申请日：2002-03-09
Applicant: 한국전자통신연구원
IPC: H01L21/8242
Abstract: PURPOSE: A method for etching a thin film and a method for manufacturing a transistor and a capacitor of a semiconductor device using the same are provided to be capable of simplifying manufacturing processes and preventing the damage of a lower layer and the generation of residues by simultaneously patterning a metal thin film and a ferroelectric thin film using a helicon plasma etching process. CONSTITUTION: After forming a lower structure at the upper portion of a semiconductor substrate(201), an SBT(SrxBi1-xTa2O9) thin film(202), a metal thin film(203), and a metal mask(204) are sequentially formed on the resultant structure. Then, the metal thin film and the SBT thin film are simultaneously patterned by carrying out a helicon plasma etching process using the metal mask as an etching mask.
Abstract translation: 目的：提供一种用于蚀刻薄膜的方法，以及使用该方法制造半导体器件的晶体管和电容器的方法，以能够简化制造工艺并且同时防止下层的损坏和残留物的产生 使用螺旋等离子体蚀刻工艺图案化金属薄膜和铁电薄膜。 构成：在半导体基板（201）的上部形成下部结构后，依次形成SBT（SrxBi1-xTa2O9）薄膜（202），金属薄膜（203）和金属掩模（204） 在所得到的结构上。 然后，通过使用金属掩模作为蚀刻掩模进行螺旋等离子体蚀刻工艺，同时对金属薄膜和SBT薄膜进行构图。
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Patent Agency Ranking
公开(公告)号：KR1020040046176A
公开(公告)日：2004-06-05
申请号：KR1020020074015
申请日：2002-11-26
Applicant: 한국전자통신연구원
IPC: H01L21/205
Abstract: PURPOSE: An apparatus for manufacturing a semiconductor device and a manufacturing method of the semiconductor device using the same are provided to be capable of effectively forming an insulating layer at a low temperature. CONSTITUTION: An apparatus for manufacturing a semiconductor device is provided with a reaction furnace(20), a wafer support part(40) installed in the reaction furnace for supporting a wafer, a heating part(50) for heating the wafer, a power supply(55) for supplying power to the heating part, and a gas flow part(10) for flowing reaction gas. The apparatus for manufacturing a semiconductor device further includes a plasma generating part(200) for transforming the reaction gas supplied from the gas flow part into ion reticle and supplying the ion reticle into the reaction furnace, and an ion removing part(300) for controlling the excessive flow of the ion reticle into the reaction furnace.
Abstract translation: 目的：提供一种用于制造半导体器件的装置和使用其的半导体器件的制造方法，以能够在低温下有效地形成绝缘层。 构成：半导体装置的制造装置具备反应炉（20），安装在用于支撑晶片的反应炉内的晶片支撑部（40），加热晶片的加热部（50），电源 （55），用于向加热部供电;以及气流部（10），用于使反应气体流动。 本发明的半导体装置的制造装置还包括：等离子体产生部（200），用于将从气体流供给的反应气体变换为离子掩模版并将离子掩模版供给到反应炉中;以及离子去除部（300） 离子掩模版过度流入反应炉。
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公开(公告)号：KR1020040041262A
公开(公告)日：2004-05-17
申请号：KR1020020069434
申请日：2002-11-09
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A pixel array for a detector having a TFT(Thin Film Transistor) structure and a manufacturing method thereof are provided to be capable of preventing the attenuation of detected gas or infrared ray information in short time due to thermal conductivity. CONSTITUTION: A pixel array for a detector is provided with a semiconductor substrate(31) having an IC(Integrated Circuit) for reading, a detecting part separated from the semiconductor substrate as much as the height of an air gap, an insulating pillar(35a) for physically connecting the detecting part with the semiconductor substrate. Preferably, the pixel array further includes a protecting layer for enclosing the detecting part. Preferably, the insulating pillar and the protecting layer are made of a silicon nitride layer. Preferably, the detecting part includes a silicon layer, a gate isolating layer(38) on the silicon layer, a gate made of a detecting layer and an absorbing layer(40), a channel region(44) in the silicon layer, and a source/drain region(41a,42a) at both sides of the gate in the silicon layer.
Abstract translation: 目的：提供一种具有TFT（薄膜晶体管）结构的检测器的像素阵列及其制造方法，其能够防止由于导热性而在短时间内检测到的气体或红外线信息的衰减。 构成：用于检测器的像素阵列设置有半导体衬底（31），该半导体衬底（31）具有用于读取的IC（集成电路），与半导体衬底分开的与气隙高度相隔的检测部分，绝缘柱（35a ），用于将检测部件与半导体基板物理连接。 优选地，像素阵列还包括用于封装检测部分的保护层。 优选地，绝缘柱和保护层由氮化硅层制成。 优选地，检测部分包括硅层，硅层上的栅极隔离层（38），由检测层制成的栅极和吸收层（40），硅层中的沟道区（44）和 源极/漏极区（41a，42a），位于硅层的栅极两侧。
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公开(公告)号：KR1020020058899A
公开(公告)日：2002-07-12
申请号：KR1020000087031
申请日：2000-12-30
Applicant: 한국전자통신연구원
IPC: G11C11/22
CPC classification number: H01L27/11502
Abstract: PURPOSE: A single transistor ferroelectric memory device is provided, which minimizes a capacitance coupling by reducing a capacitance between adjacent wells, and minimizes an RC delay time by reducing a resistance of the well. CONSTITUTION: A p+ doped layer(402) is formed on an n silicon substrate(401), and a p well(403) is formed thereon. An n+ source/drain(404) is formed on a surface of the p well, and a ferroelectric transistor is constituted by stacking a ferroelectric thin film and a gate electrode on the p well between the source and the drain. And a p+ diffusion layer(408) is formed by being separated from the source/drain by a field oxide(407b) on the surface of the p well. A metal layer(410) is contacted to the n+ source/drain and the p+ diffusion layer through an interlayer insulation film(409) respectively. A trench oxide(411) is formed into a fixed depth of the n silicon substrate by penetrating the p+ doped layer from the surface of the p well. Because a pulse voltage is applied to each port independently by the trench oxide, an electrical disturb from a device array of an adjacent column is prevented during a read/write operation.
Abstract translation: 目的：提供单晶体管铁电存储器件，其通过减小相邻阱之间的电容来最小化电容耦合，并且通过降低阱的电阻来最小化RC延迟时间。 构成：在n硅衬底（401）上形成p +掺杂层（402），并在其上形成p阱（403）。 在p阱的表面上形成n +源极/漏极（404），并且通过在源极和漏极之间的p阱上堆叠铁电薄膜和栅极电极来构成铁电晶体管。 并且通过在p阱的表面上的场氧化物（407b）与源极/漏极分离而形成p +扩散层（408）。 金属层（410）分别通过层间绝缘膜（409）与n +源极/漏极和p +扩散层接触。 通过从p阱的表面穿透p +掺杂层，将沟槽氧化物（411）形成为n硅衬底的固定深度。 由于脉冲电压被沟槽氧化物独立地施加到每个端口，所以在读/写操作期间防止来自相邻列的器件阵列的电干扰。
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公开(公告)号：KR1020020044312A
公开(公告)日：2002-06-15
申请号：KR1020000073340
申请日：2000-12-05
Applicant: 한국전자통신연구원
CPC classification number: G11C13/025 , B82Y10/00 , G11C2213/81
Abstract: PURPOSE: Data storage media are provided to use carbon nanotubes for reducing interferences between neighboring magnetic substances, generated as bit size of magnetic media is smaller and nearer, thereby increasing data stability. CONSTITUTION: A porous material(120) is accumulated on a substrate(110). A ferromagnetic material(140) is contained in porous parts of the porous material, and causes a magnetic polarization phenomenon, to perform magnetic recording media functions. An information recorder applies a magnetic field to the ferromagnetic material, to generate magnetic polarization in the ferromagnetic material, and records information. An information reader extracts an effect of the magnetic polarization of the ferromagnetic material, and reads out an information state in accordance with a polarization direction.
Abstract translation: 目的：提供数据存储介质以使用碳纳米管来减少相邻磁性物质之间的干扰，由磁性介质的位大小产生，从而增加数据的稳定性。 构成：多孔材料（120）积聚在基底（110）上。 铁氧体材料（140）被包含在多孔材料的多孔部分中并引起磁极化现象，从而执行磁记录介质的功能。 信息记录器对铁磁材料施加磁场，在铁磁材料中产生磁极化，并记录信息。 信息读取器提取铁磁材料的磁极化的影响，并且根据偏振方向读出信息状态。
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公开(公告)号：KR1020020033301A
公开(公告)日：2002-05-06
申请号：KR1020000063959
申请日：2000-10-30
Applicant: 한국전자통신연구원
IPC: G11C11/22
CPC classification number: G11C11/2273 , G11C5/025 , G11C7/12 , G11C11/2253 , G11C11/2275 , G11C11/2297
Abstract: PURPOSE: A single transistor ferroelectric memory and a method for driving the same are provided to prevent a write disturbing effect of a non-selected cell by a word line. CONSTITUTION: A main control portion(50) is used for generating basic control signals of a single transistor ferroelectric memory. A word line control portion(52) and a source line control portion(53) are used for selecting particular cells according to input addresses and generating voltages for selected cells. A read voltage generation portion(51) is used for generating a read voltage when a read operation is performed. A word line selection portion(54) is used for applying selectively the voltage to the selected word line. A multitude of word line, a multitude of bit line, a source line, and a ferroelectric transistor are formed on a memory cell array(55). A bit line control portion(56) is used for determining a type of memory output. A sense amplifier portion(57) is used for sensing the voltage of the selected cell and the voltage of non-selected cell when the read operation is performed.
Abstract translation: 目的：提供单晶体管铁电存储器及其驱动方法，以通过字线来防止未选择的单元的写入干扰效应。 构成：主控制部分（50）用于产生单晶体管铁电存储器的基本控制信号。 字线控制部分（52）和源极线控制部分（53）用于根据输入的地址选择特定的单元并产生所选择的单元的电压。 读取电压产生部分（51）用于在执行读取操作时产生读取电压。 字线选择部分（54）用于选择性地将电压施加到所选择的字线。 多个字线，多个位线，源极线和铁电晶体管形成在存储单元阵列（55）上。 位线控制部分（56）用于确定存储器输出的类型。 当执行读取操作时，读出放大器部分（57）用于感测所选择的单元的电压和非选择单元的电压。
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