中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

115 records (took 0.019 seconds)

    82.
    发明专利
    未知

    公开(公告)号：DE10296953T5

    公开(公告)日：2004-04-29

    申请号：DE10296953

    申请日：2002-06-06

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  IEONG MEIKEI ,  MULLER K PAUL ,  NOWAK EDWARD J ,  FRIED DAVID M ,  RANKIN JED

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/28

    Abstract: A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

    Strained fin fets structure and method
    83.
    发明专利
    Strained fin fets structure and method 未知

    公开(公告)号：AU2003223306A8

    公开(公告)日：2003-10-08

    申请号：AU2003223306

    申请日：2003-03-19

    Applicant: IBM

    Inventor： NOWAK EDWARD J ,  CLARK WILLIAM F ,  LANZEROTTI LOUIS D ,  FRIED DAVID M

    IPC: H01L21/336 ,  H01L29/10 ,  H01L29/786 ,  H01L29/78 ,  H01L33/00

    Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.

    A FIELD EFFECT TRANSISTOR AND A METHOD FOR MANUFACTURING THE SAME
    84.
    发明专利
    A FIELD EFFECT TRANSISTOR AND A METHOD FOR MANUFACTURING THE SAME 未知

    公开(公告)号：HK1026064A1

    公开(公告)日：2000-12-01

    申请号：HK00105169

    申请日：2000-08-17

    Applicant: IBM

    Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  ELLIS-MONAGHAN JOHN J ,  MACIEJEWSKI EDWARD P ,  NOWAK EDWARD J ,  PRICER WILBUR D ,  TONG MINH H

    IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L

    Abstract: A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

    Semiconductor structure and methods of manufacture
    87.
    发明专利
    Semiconductor structure and methods of manufacture 未知

    公开(公告)号：GB2498675A

    公开(公告)日：2013-07-24

    申请号：GB201307733

    申请日：2011-09-06

    Applicant: IBM

    Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J

    IPC: H01L29/78

    Abstract: FinFET end-implanted-semiconductor structures and methods of manufacture are disclosed herein. The method includes forming at least one mandrel (14 in Fig. 5) on a silicon layer of a substrate (18') comprising an underlying insulator layer (10b). The method further includes etching the silicon layer to form at least one silicon island (18') under the at least one mandrel. The method further comprises ion- implanting sidewalls of the at least one silicon island to form doped regions (20) on the sidewalls. The method further includes forming a dielectric layer on the substrate, a top surface of which is planarized to be coplanar with a top surface of the at least one mandrel (14). The method further includes removing the at least one mandrel (14) to form an opening in the dielectric layer. The method further comprises etching the at least one silicon island to form at least one fin island having doped source and drain regions.

    FET WITH REPLACEMENT GATE STRUCTURE AND METHOD OF FABRICATING THE SAME
    88.
    发明专利
    FET WITH REPLACEMENT GATE STRUCTURE AND METHOD OF FABRICATING THE SAME 未知

    公开(公告)号：SG176539A1

    公开(公告)日：2012-01-30

    申请号：SG2011089075

    申请日：2010-06-02

    Applicant: IBM

    Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J

    Abstract: A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates (16 of FIG. 6) about a plurality of active regions and depositing a dielectric material (18a and in space 20) over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions of the dielectric material (20) to expose the temporary spacer gates (16) and removing the temporary spacer gates, leaving a space between the active regions and a remaining portion of the dielectric material (18a). The method additionally includes filling the space (20) between the active regions and above the remaining portion of the dielectric material (18a) with a gate material.

    THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION
    89.
    发明专利
    THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION 未知

    公开(公告)号：CA2750215A1

    公开(公告)日：2010-11-04

    申请号：CA2750215

    申请日：2010-04-22

    Applicant: IBM

    Inventor： GREENE BRIAN J ,  CHUDZIK MICHAEL P ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  LIANG YUE ,  MACIEJEWSKI EDWARD P ,  NA MYUNG-HEE ,  NOWAK EDWARD J ,  YU XIAOJUN

    IPC: H01L21/71 ,  H01L21/77 ,  H01L27/085 ,  H01L27/098

    Abstract: Multiple types of gate stacks (100,..., 600) are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric (30L) is formed on the doped semiconductor well (22, 24). A metal gate layer (42L) is formed in one device area, while the high-k gate dielectric is exposed in other device areas (200, 400, 500, 600). Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer (72L) is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

Patent Agency Ranking