公开(公告)号：WO2007046271A1

公开(公告)日：2007-04-26

申请号：PCT/JP2006/320219

申请日：2006-10-10

Applicant: 日本電気株式会社 ,  クシュタ タラス ,  成田 薫

Inventor： クシュタ タラス ,  成田 薫

IPC: H01P3/06 ,  H01L23/12 ,  H05K3/46

CPC classification number: H05K1/0222 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6622 ,  H01L2224/16235 ,  H01L2924/01004 ,  H01L2924/01057 ,  H01L2924/01087 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/115 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718

Abstract: 　多層ＰＣＢにおいて、広い周波数帯域にわたり高度の電気特性および遮蔽特性を有する垂直信号経路、その垂直信号経路を有するプリント基板及びそのプリント基板と半導体素子とを有する半導体パッケージを提供する。 　多層ＰＣＢ用の垂直信号経路において、１つの導波チャンネルが、少なくとも１つ以上の信号バイア２０１と、その信号バイアの周囲の接地バイア２０２の集合と、接地バイアに接続されたＰＣＢ導体層からなる接地プレートと、接地バイアと接続する閉じた接地ストリップ線路２０５と、接地ストリップ線路と電源層からなる導体平面との間の絶縁スロット２０６によって形成される。クリアランスホール２０３と呼ばれる、垂直信号経路における少なくとも１つ以上の信号バイアと接地素子の間の空隙は、ＰＣＢの絶縁素材で充填することができる。

Abstract translation: 提供了一种在多层PCB中的宽频带上具有高电特性和屏蔽特性的垂直信号路径，具有这种垂直信号路径的印刷板以及具有这种印刷板和半导体元件的半导体封装。 在多层PCB的垂直信号路径中，一个波导通道由至少一个信号通路（201）组成; 围绕信号通孔的一组接地通孔（202）; 接地板由与接地通孔连接的PCB导体层组成; 与接地通孔连接的封闭接地带线路（205）; 以及在接地带线和由电源层组成的导体平面之间的绝缘槽（206）。 可以用PCB绝缘材料填充在垂直信号路径中的至少一个信号通孔和接地元件之间的称为间隙孔（203）的空间。

公开(公告)号：WO2003073812A1

公开(公告)日：2003-09-04

申请号：PCT/US2002/027986

申请日：2002-09-03

Applicant: FORCE10 NETWORKS, INC.

Inventor： GOERGEN, Joel, R.

IPC: H05K3/46

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.

Abstract translation: 所公开的板制造技术和设计特征使得能够构建用于路由器等的可靠的，高层次的和经济的背板，其需要以2.5Gbps或更高的速度跨越背板的大量信令路径，以及 作为路由器组件的大量功率分配。 所公开的技术和特征允许相对较厚（例如，三或四盎司铜）功率分配平面与公共背板中的大量高速信号层组合。 使用传统技术，由于需要的层数和配电层的厚度，这种结构将是不可能的。 所公开的实施例使用新颖的层布置，材料选择，处理技术和面板特征来在单个机械稳定的板中产生期望的高速层和低噪声大功率分配层。

公开(公告)号：WO01076336A1

公开(公告)日：2001-10-11

申请号：PCT/CH2001/000201

申请日：2001-03-30

IPC: H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/00 ,  H05K3/04 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40 ,  H05K3/46

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/0263 ,  H05K1/0268 ,  H05K1/0272 ,  H05K1/0274 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K1/144 ,  H05K1/162 ,  H05K1/185 ,  H05K3/005 ,  H05K3/0055 ,  H05K3/0061 ,  H05K3/041 ,  H05K3/046 ,  H05K3/3436 ,  H05K3/368 ,  H05K3/4084 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2201/10598 ,  H05K2203/0108 ,  H05K2203/0195 ,  H05K2203/0285 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00

Abstract: According to the invention, a microperforation (PMP) process step is combined with the lamination process. To this end, a dielectric layer (11,11') and a prefabricated product (1) are placed between two perforation dies (21,23) or a support and a perforation die. The prefabricated product (1) is partially covered by a conducting layer forming structures to be contacted by microvias. Pressure is applied on the perforation die (21,22), perforation tips of the perforation dies forming microvias for contacting the structures. A surface of the dielectric layer (11,11') or the prefabricated product (1) is configurated or coated to in a manner that the prefabricated product (1) and the dielectric layer (11,11') stick to each other after the pressure has been applied.

Abstract translation: 根据本发明，将微穿孔（PMP）工艺步骤与层压工艺组合。 为此，将介电层（11,11'）和预制产品（1）放置在两个穿孔模具（21,23）或支撑件和穿孔模具之间。 预制产品（1）被形成由微孔接触的导电层部分覆盖。 在穿孔模具（21,22）上施加压力，穿孔模具的穿孔尖端形成用于接触结构的微孔。 电介质层（11,11'）或预制产品（1）的表面被构造或涂覆，使得预制产品（1）和电介质层（11,11'）之间彼此粘合 压力已被应用。

公开(公告)号：WO2008003021A2

公开(公告)日：2008-01-03

申请号：PCT/US2007072321

申请日：2007-06-28

Applicant: INTEL CORP ,  LEADER BRAM ,  DOERSCH RICHARD

Inventor： LEADER BRAM ,  DOERSCH RICHARD

CPC classification number: H05K1/0222 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09636 ,  H05K2201/09809 ,  H01L2924/00

Abstract: A system may include a first conductive ground pad, a second conductive ground pad, a first conductive via coupling the first ground pad to the second ground pad, a first conductive signal trace, a second conductive signal trace, and a second conductive via disposed within the first conductive via and coupling the first conductive signal trace to the second conductive signal trace. The first conductive ground pad and the second conductive ground pad may be disposed between the first conductive signal trace and the second conductive signal trace.

Abstract translation: 系统可以包括第一导电接地焊盘，第二导电接地焊盘，将第一接地焊盘耦合到第二接地焊盘的第一导电通孔，第一导电信号迹线，第二导电信号迹线和设置在第二接地焊盘内的第二导电通孔 第一导电通孔并将第一导电信号迹线耦合到第二导电信号迹线。 第一导电接地焊盘和第二导电接地焊盘可以设置在第一导电信号迹线和第二导电信号迹线之间。

公开(公告)号：WO2007102597B1

公开(公告)日：2007-11-08

申请号：PCT/JP2007054621

申请日：2007-03-02

Applicant: NEC CORP ,  NEC ELECTRONICS CORP ,  KUSHTA TARAS ,  NARITA KAORU ,  KANEKO TOMOYUKI ,  OGOU SHIN-ICHI

Inventor： KUSHTA TARAS ,  NARITA KAORU ,  KANEKO TOMOYUKI ,  OGOU SHIN-ICHI

IPC: H05K3/46

CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09381 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09727

Abstract: According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; The length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.

Abstract translation: 根据一个实施例，形成多层衬底中的将通孔结构和平面传输线接合的宽带过渡作为信号通孔焊盘与布置在相同导体层上的平面传输线之间的中间连接。 过渡部分的横向尺寸等于一端的通孔焊盘直径和另一端的焊条宽度; 根据通过三维全波模拟获得的数字图，过渡的长度可以等于间隙孔在平面传输线方向上的特征尺寸或者被定义为在时域中提供最小过量感抗 。

公开(公告)号：WO2005081595A3

公开(公告)日：2005-12-15

申请号：PCT/US2005004468

申请日：2005-02-14

Applicant: MOLEX INC

Inventor： REGNIER KENT E ,  BRUNKER DAVID L ,  OGBUOKIRI MARTIN U

IPC: H01L23/64 ,  H01L23/66 ,  H01R12/16 ,  H01R13/658 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H01R24/00

CPC classification number: H05K1/0245 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10189 ,  H01L2924/00

Abstract: A circuit board (200, 300, 400) design is disclosed that is useful in high speed differential signal applications uses either a via arrangement or a circuit trace exit structure. In the via arrangement, sets of differential signal pair vias (301, 303, 401, 402) and an associated ground (302) are arranged adjacent to each other in a repeating pattern. The differential signal vias (301, 303, 591) of each pair are spaced closer to their associated ground via (302a, 593a) than the spacing between the adjacent differential signal pair associated ground (302b, 593b) so that differential signal vias exhibit a preference for electrically coupling to their associated ground vias. The circuit trace exit structure involves the exit portions of the circuit traces (420, 550) of the differential signal vias (401, 402, 591) to follow a path where the traces then meet with and join to the transmission line portions (552) of the conductive traces.

Abstract translation: 公开了一种在高速差分信号应用中使用通路布置或电路走线出口结构的电路板（200,300,400）设计。 在通孔布置中，差分信号对通孔（301,303,401,402）和相关联的接地（302）的组以重复图案彼此相邻布置。 每对的差分信号通孔（301,303,591）比相邻的差分信号对相关联的接地（302b，593b）之间的间隔更靠近其相关联的接地（302a，593a），使得差分信号通孔显示出 优选电耦合到其相关的接地通孔。 电路走线出口结构涉及差分信号通孔（401,402,591）的电路迹线（420,550）的出口部分，以跟随走线然后与路线相交并连接到传输线部分（552）的路径， 的导电迹线。

公开(公告)号：WO2005081595A2

公开(公告)日：2005-09-01

申请号：PCT/US2005/004468

申请日：2005-02-14

Applicant: MOLEX INCORPORATED

Inventor： REGNIER, Kent, E. ,  BRUNKER, David, L. ,  OGBUOKIRI, Martin, U.

IPC: H05K1/00

CPC classification number: H05K1/0245 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/10189 ,  H01L2924/00

Abstract: A circuit board design is disclosed that is useful in high speed differential signal applications uses either a via arrangement or a circuit trace exit structure. In the via arrangement, sets of differential signal pair vias and an associated ground are arranged adjacent to each other in a repeating pattern. The differential signal vias of each pair are spaced closer to their associated ground via than the spacing between the adjacent differential signal pair associated ground so that differential signal vias exhibit a preference for electrically coupling to their associated ground vias. The circuit trace exit structure involves the exit portions of the circuit traces of the differential signal vias to follow a path where the traces then meet with and join to the transmission line portions of the conductive traces.

Abstract translation: 公开了一种在高速差分信号应用中使用电路布置或电路走线出口结构的电路板设计。 在通孔布置中，差分信号对通孔和相关接地的组以重复图案彼此相邻布置。 每对的差分信号通孔比相邻的差分信号对相关联的接地之间的间隔更靠近其相关联的接地间隔，使得差分信号通孔表现出对它们相关的接地通孔的电耦合的偏好。 电路走线出口结构涉及差分信号通孔的电路迹线的出口部分，以跟随路径，其中迹线然后与导电迹线的传输线部分相接合并连接到导体迹线的传输线部分。

公开(公告)号：WO2003073808A1

公开(公告)日：2003-09-04

申请号：PCT/US2002/027987

申请日：2002-09-03

Applicant: FORCE 10 NETWORKS, INC.

Inventor： GOERGEN, Joel, R.

IPC: H05K1/02

CPC classification number: H05K1/0245 ,  H05K1/0248 ,  H05K1/116 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4641 ,  H05K7/1459 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: A high-speed router backplane, and method for its fabrication, are disclosed. The backplane uses differential signaling trace pairs on multiple high-speed signaling layers, the high-speed signaling layers separated by ground planes. Plated signaling thru-holes connect the trace pairs to the board surface for connection to external components. The signaling thru-holes pass through clearances in each ground plane. At selected ground planes, a conductive pad is patterned within each high-speed signaling thru-hole clearance, the pad slightly larger than the thru-hole diameter. The pads affect the impedance characteristics of the thru-holes, thus providing a better impedance match to the differential trace pairs, reducing signal reflections, and improving the ability to signal across the backplane at high speeds.

Abstract translation: 公开了一种高速路由器背板及其制造方法。 背板在多个高速信号层上使用差分信令跟踪对，高速信号层由接地层分开。 电镀信号通孔将走线对连接到电路板表面，以连接到外部组件。 信号通孔穿过每个接地平面内的间隙。 在选定的接地平面，每个高速信号通孔间隙内的导电焊盘都被图案化，焊盘略大于通孔直径。 这些焊盘影响通孔的阻抗特性，从而为差分走线对提供更好的阻抗匹配，减少信号反射，并提高高速信号跨背板的能力。

公开(公告)号：WO2003067906A2

公开(公告)日：2003-08-14

申请号：PCT/US2002/027999

申请日：2002-09-03

Applicant: FORCE10 NETWORKS, INC.

Inventor： GOERGEN, Joel, R.

IPC: H04Q1/10

CPC classification number: H05K1/0245 ,  H04Q1/03 ,  H04Q1/10 ,  H04Q1/155 ,  H04Q2201/12 ,  H05K3/4641 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09354 ,  H05K2201/09636

Abstract: A high-speed, high-power modular router is disclosed. As opposed to conventional designs using optical backplane signaling and/or bus bars for power distribution, the disclosed embodiments combine high-power, low-noise power distribution with high-speed signal routing in a common backplane. Disclosed backplane features allow backplane signaling at 2.5 Gbps or greater on electrical differential pairs distributed on multiple high-speed signaling layers. Relatively thick power distribution layers are embedded within the backplane, shielded from the high-speed signaling layers by digital ground layers and other shielding features. A router using such a backplane provides a level of performance and economy that is believed to be unattainable by the prior art.

Abstract translation: 公开了一种高速，高功率模块化路由器。 与使用光学背板信号传输和/或母线进行配电的常规设计相反，所公开的实施例将高功率，低噪声功率分配与高速信号路由结合在公共背板中。 公开的背板功能允许在分布在多个高速信令层上的电气差分对上以2.5 Gbps或更高的背板信号传输。 相对较厚的配电层嵌入在背板内，通过数字接地层和其他屏蔽功能与高速信号层隔离。 使用这种背板的路由器提供了现有技术无法达到的性能和经济水平。

公开(公告)号：WO2015096401A1

公开(公告)日：2015-07-02

申请号：PCT/CN2014/079463

申请日：2014-06-09

Applicant: 京东方科技集团股份有限公司

Inventor： 邵继洋 ,  郑喆奎 ,  栗首 ,  赵天月

IPC: H05K1/11 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K2201/09609 ,  H05K2201/09636

Abstract: 公开了一种电路板及其制作方法，该电路板包括第一信号传输层和第二信号传输层，所述电路板还包括：设置于所述第一信号传输层的多个第一信号传输单元；在所述第二信号传输层对应于所述多个第一信号传输单元设置的多个第二信号传输单元；对应于每一个第一信号传输单元对应设置的过孔单元（3011），其中：对应的第一信号传输单元和第二信号传输单元通过对应的过孔单元（3011）形成电连接；所述过孔单元（3011）分为至少两行排列，形成至少两个过孔行（301）；在平行于所述过孔行（301）的方向上，相邻的过孔行（301）之间形成一偏移，且在所述第一信号传输层内垂直于所述过孔行（301）的方向上，相邻的过孔行（301）之间存在交叠的部分。提高了电路板的信号传输质量。