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    Bond pads for fine-pitch applications on air bridge circuit boards
    82.
    发明公开
    Bond pads for fine-pitch applications on air bridge circuit boards 审中-公开
    对于与中途停留的印刷电路板具有细间距应用接触表面

    公开(公告)号：EP1026928A2

    公开(公告)日：2000-08-09

    申请号：EP00300553.5

    申请日：2000-01-26

    Applicant: Ford Motor Company

    Inventor： Goenka, Lakhi Nandial

    IPC: H05K1/11

    CPC classification number: H05K1/111 ,  H05K3/062 ,  H05K3/4685 ,  H05K2201/0361 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09736 ,  H05K2201/09772 ,  H05K2201/098 ,  Y02P70/611

    Abstract: An etched tri-metal-layer air bridge circuit board specially designed for fine-pitch applications, comprising:

    an electrically insulative substrate surface (10), a plurality of tri-metal-layer bond pads (12) arranged in a generally straight row on the substrate surface (10) wherein the row defines a width direction therealong, and a circuit trace (20) arranged on the substrate surface (10), wherein the circuit trace (20) runs between two adjacent ones (22) of the plurality of tri-metal-layer bond pads (12). Each bond pad (12) comprises: (1) a bottom layer (14) attached to the substrate surface (10), the bottom layer (14) being made of a first metal and having an overall width W1 as measured along the width direction; (2) a top layer (18) disposed above and generally concentric with the bottom layer (14), the top layer (18) being made of the first metal and having an overall width W2 as measured along the width direction; and (3) a middle layer (16) made of a second metal connecting the bottom layer (14) and the top layer (18). The bond pads (12) are specially shaped such that W2 > W1 for at least the two adjacent bond pads (12), thus enabling the circuit trace (20) to be spaced closely to the bottom layers (14) of the two adjacent bond pads (12), while allowing the top layers (18) of the pads (12) to be made much larger so as to avoid delamination thereof from their associated middle layers (16).

    Abstract translation: 蚀刻的三金属层的空气桥电路板专为细间距应用，包括：在一个基因的反弹直排布置在电绝缘衬底表面（10），的三金属层接合垫有多个（12） 配置于该基板表面（10）worin的电路迹线（20）在基片上表面（10）worin行有沿定义的宽度方向，和一个电路迹线（20）的所述多个相邻的两个（22）之间延伸 三金属层接合焊盘（12）。 每一接合垫（12）包括：（1）附连到基板表面（10）的底层（14），底层（14）由第一金属制成的，并沿宽度方向测量的具有总宽度W1 ; 上述（2）和基因反弹同心设置为与底层（14），所述顶层（18）的顶层（18）由所述第一金属的，并具有为沿宽度方向测量的总宽度W2; 和（3）由第二金属制成的连接底部层（14）和顶层（18）的中间层（16）。 的键合焊盘（12）被特殊形状搜索做W2> W1，至少在两个相邻的键合焊盘（12）从而使电路迹线（20）被紧密间隔相邻的两个键的底层（14） 垫（12），同时允许所述垫（12）的顶层（18），以进行大得多，以便从它们相关联的中间层（16），其避免脱层。

    Capacitor mounting structure for printed circuit boards
    84.
    发明公开
    Capacitor mounting structure for printed circuit boards 失效
    Montagestruktur von KondensatorenfürLeiterplatten。

    公开(公告)号：EP0617568A1

    公开(公告)日：1994-09-28

    申请号：EP94301987.7

    申请日：1994-03-21

    Applicant: Compaq Computer Corporation

    Inventor： Stoddard, D Joe

    IPC: H05K1/11

    CPC classification number: H05K3/3442 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K3/0094 ,  H05K2201/0792 ,  H05K2201/09772 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

    Abstract: A capacitor mounting structure for printed circuit boards wherein the capacitor includes first and second terminals (15a,15b) which are connected to first and second conductor planes (44,45) in the printed circuit board (B). Three vias (41,42,43) are mounted in the printed circuit board (B) in a position to be aligned with the middle of the capacitor. A first conductor pad (45) is mounted underneath one end of the capacitor and includes spaced apart extension portions (45b,45c) which electrically attach to the first (41) and third via (43). A second conductor pad (44) is mounted under the other end of the capacitor and includes a central extension portion (44b) which attaches to the second or middle via (42). In this manner, the region available for generation of parasitic inductance is minimized thereby increasing the operating efficiency of the capacitor.

    Abstract translation: 一种用于印刷电路板的电容器安装结构，其中电容器包括连接到印刷电路板（B）中的第一和第二导体平面（44,45）的第一和第二端子（15a，15b）。 三个通孔（41,42,43）安装在印刷电路板（B）中以与电容器的中间对准的位置。 第一导体焊盘（45）安装在电容器的一端下方，并且包括电连接到第一（41）和第三通孔（43）的间隔开的延伸部分（45b，45c）。 第二导体焊盘（44）安装在电容器的另一端之下，并且包括连接到第二或中间通孔（42）的中心延伸部分（44b）。 以这种方式，可用于产生寄生电感的区域被最小化，从而提高了电容器的工作效率。

    Heating apparatus for heating electronic components on a printed circuit board in low temperature environment
    88.
    发明公开
    Heating apparatus for heating electronic components on a printed circuit board in low temperature environment 审中-公开
    用于在低温环境下在电路板上加热电子部件的加热装置

    公开(公告)号：EP2693851A1

    公开(公告)日：2014-02-05

    申请号：EP12005535.5

    申请日：2012-07-30

    Applicant: Mildef Crete Inc.

    Inventor： Chou, Chih-Sheng

    IPC: H05K1/02

    CPC classification number: H05K1/0212 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10151 ,  H05K2201/10166

    Abstract: A heating apparatus for heating electronic components (11) on a printed circuit board (1) in low temperature environment includes a printed circuit board (1), a heating unit (2), a switch unit (3), a temperature-sensing unit (4), an electric power unit (5), and a control unit (6). The heating unit (2), the switch unit (3), the temperature-sensing unit (4), and the control unit (6) are fixed connected to the printed circuit board (1) and are electrically connected with the metal lines (12) on the printed circuit board (1). The heat source is sent to the heat-conducting layer (14) on the printed circuit board (1) through the heat-conducting terminal (22) after the switch unit (3) is conducted by the control unit (6) and the power is sent from the electric power unit (5) to the heating unit (2). Then, the electronic components (11) are heated with the heat source through the heat-conducting layer (14), so that the electronic components (11) are in the working temperatures for starting up.

    Abstract translation: 对在低温环境中的印刷电路板（1）加热的电子部件（11）的加热装置包括：印刷电路板（1），一个加热单元（2），开关单元（3），温度感测单元 （4）一种电动动力单元（5），以及控制单元（6）。 所述加热单元（2），开关单元（3），所述温度感测单元（4），并且所述控制单元（6）被固定连接到印刷电路板（1），并与金属线电连接（ 12）在所述印刷电路板（1）。 热源被发送到在印刷电路板（1）通过开关单元后的热传导端（22）的热传导层（14）（3）由控制单元传导（6）和所述功率 从电源装置（5）向加热单元（2）发送。 然后，将电子部件（11）是通过所述导热层（14）中的热源加热，所以做了电子部件（11）是在用于启动的工作温度。

    VORRICHTUNG ZUR FEHLERSTROMERKENNUNG IN EINEM ELEKTRONISCHEN GERÄT
    89.
    发明公开
    VORRICHTUNG ZUR FEHLERSTROMERKENNUNG IN EINEM ELEKTRONISCHEN GERÄT 有权
    设备技术故障电流检测的电子设备中

    公开(公告)号：EP1932400A1

    公开(公告)日：2008-06-18

    申请号：EP06792843.2

    申请日：2006-08-16

    Applicant: ROBERT BOSCH GMBH

    Inventor： KNAB, Norbert ,  BREITLING, Wolfram

    IPC: H05K1/02

    CPC classification number: H05K1/0268 ,  H05K1/0256 ,  H05K3/202 ,  H05K2201/0761 ,  H05K2201/09236 ,  H05K2201/09772

    Abstract: The invention proposes an apparatus (10) for detecting fault currents in an electronic device (12), having at least one first electrical conductor (16), which carries a first electrical potential (V1), and having a sense conductor (22), which has an electrical open-circuit potential (VR), which is between the first electrical potential (V1) and a further electrical potential (V2). The apparatus (10) according to the invention is characterized by the fact that the at least one first electrical conductor (16) and the sense conductor (22) are arranged spaced apart from one another on and/or in an insulating material (24), wherein, in the event of a fault, a reduction in the insulating properties of the insulating material (24) can be identified by means of the sense conductor (22) owing to a shift in the electrical open-circuit potential (VR).

    DATA BUS CONNECTION FOR MEMORY DEVICE
    90.
    发明授权
    DATA BUS CONNECTION FOR MEMORY DEVICE 有权
    数据总线连接用于存储器安排

    公开(公告)号：EP1449412B1

    公开(公告)日：2007-10-31

    申请号：EP02790420.0

    申请日：2002-11-21

    Applicant: Thomson Licensing

    Inventor： LI, Hua ,  CHIN, Yuan Fuat

    IPC: H05K1/00

    CPC classification number: H05K1/181 ,  H05K2201/09236 ,  H05K2201/09772 ,  H05K2201/10689 ,  Y02P70/611

    Abstract: A data bus of a DVD+RW recorder between a DSP and a SDRAM usually needs a multilayer wiring board. In order to simplify the layout of the wiring board of the data bus there is provided a method for connecting at least a first and a second integrated circuit by providing the first integrated circuit having a plurality of first logical I/O ports physically arranged in a first order at the periphery, and providing the second integrated circuit having a plurality of second logical I/O ports physically arranged in a second order at the periphery, wherein each first I/O port is to be connected to one of said second I/O ports. The first and second I/O logical ports are connected independently from the first and/or second physical order, so that connection lines do not cross each other.

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