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公开(公告)号：KR1020090079696A
公开(公告)日：2009-07-22
申请号：KR1020080005854
申请日：2008-01-18
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H05H1/26 , H01L21/205
CPC classification number: H01J37/3211 , H01J37/32183 , H01J37/32431 , H01J37/32715 , H01Q1/366 , H05H1/46 , H05H2001/2412 , H05H2001/4667 , H05H2001/4682
Abstract: A plasma processing apparatus having linear antennas is provided to improve density uniformity of plasma by changing a thickness of a dielectric for surrounding the linear antenna. A plasma processing apparatus having linear antennas includes a reaction chamber(110), a substrate supporting plate(120), linear antennas(132), an RF power source(138), and a dielectric(142). The substrate supporting plate is installed in a lower side of the inside of the reaction chamber in order to support a substrate to be processed. The linear antennas are used for inducing electric field to generate electric field. The linear antennas are installed in parallel to each other at an upper side of the inside of the reaction chamber. The RF power source is connected to the linear antennas in order to supply RF power to the linear antennas. The dielectric is formed to surround each of the linear antennas. The thickness of the dielectric is gradually reduced from a RF power input terminal of each linear antenna to a grounding terminal(132b).
Abstract translation: 提供具有线性天线的等离子体处理装置，通过改变用于包围线状天线的电介质的厚度来改善等离子体的密度均匀性。 具有线性天线的等离子体处理装置包括反应室（110），基板支撑板（120），线性天线（132），RF电源（138）和电介质（142）。 基板支撑板安装在反应室内侧的下侧，以便支撑待处理的基板。 线性天线用于感应电场以产生电场。 线性天线在反应室内部的上侧彼此平行地安装。 RF电源连接到线性天线，以便向线性天线提供RF功率。 电介质形成为围绕每个线性天线。 电介质的厚度从每个线性天线的RF功率输入端逐渐减小到接地端子（132b）。
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公开(公告)号：KR101186292B1
公开(公告)日：2012-09-27
申请号：KR1020060002687
申请日：2006-01-10
Applicant: 삼성전자주식회사
IPC: H01L29/786 , H05B33/00
CPC classification number: H01L29/78645 , H01L27/1288 , H01L27/3244 , H01L29/78624 , H01L29/78696
Abstract: 트랜지스터와 트랜지스터의 제조방법 및 이를 이용하는 유기발광디스플레이에 관해 개시된다. 개시된 트랜지스터는 상호 나란하게 배치되어 각 양단에 도핑된 고전도 영역과 양 고전도 영역 사이의 채널 영역을 각각 가지는 두 개의 다결정 실리콘층; 두 다결정 실리콘층을 공히 가로지르는 방향으로 연장되는 게이트; 그리고 상기 게이트와 상기 다결정 실리콘층들의 사이에 개재되는 게이트 절연층;을 구비하고, 상기 게이트의 일측 가장자리에 인접하여 마련되는 것으로 다결정 실리콘의 채널 영역과 고전도 영역 사이에는 상호 마주 보는 저전도영역이 형성되어 있는 구조를 갖는다. 구조적으로 길이가 연장된 채널을 가지며 그리고 마스크 없이 형성가능한 오프셋구조 또는 저도핑영역을 갖는다.
OLED, 다결정,TFT, LDD-
公开(公告)号：KR1020110045257A
公开(公告)日：2011-05-04
申请号：KR1020090101733
申请日：2009-10-26
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/4232 , H01L21/02225 , H01L21/823412 , H01L29/41725
Abstract: PURPOSE: A transistor using a myelin layer is provided to form a gate insulating film, thereby operating a transistor with a low voltage. CONSTITUTION: A gate insulating film(130) includes a myelin layer. The gate insulating film is adjacent to a gate(120). A channel layer(140) is separated from the gate by the gate insulating film. The channel layer is formed of an organic semiconductor. A source(150) and a drain(160) are formed on both sides of the channel layer.
Abstract translation: 目的：提供使用髓磷脂层的晶体管以形成栅极绝缘膜，从而操作具有低电压的晶体管。 构成：栅绝缘膜（130）包括髓鞘层。 栅极绝缘膜与栅极（120）相邻。 沟道层（140）通过栅极绝缘膜与栅极分离。 沟道层由有机半导体形成。 源极（150）和漏极（160）形成在沟道层的两侧。
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公开(公告)号：KR1020090056590A
公开(公告)日：2009-06-03
申请号：KR1020070123809
申请日：2007-11-30
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02614 , H01L21/02631 , H01L21/02233
Abstract: A fabrication method of an oxide semiconductor thin film transistor is provided to control excess on the surface of a channel easily by process the surface of the channel with a wet oxidizer. An oxide semiconductor channel(22a), a source electrode(23a) and a drain electrode(23b) connected to the both sides of channel layer are formed on a substrate(10). The surface of a channel is oxidized by contacting an oxide material on the channel surface. The oxide material is one of a liquid oxidizer and SAM(Self Assembled Monolayer) on the channel surface.
Abstract translation: 提供氧化物半导体薄膜晶体管的制造方法，通过用湿氧化剂处理通道的表面，容易地控制通道表面上的过量。 在基板（10）上形成氧化物半导体沟道（22a），连接到沟道层两侧的源电极（23a）和漏电极（23b）。 通道的表面通过在通道表面上接触氧化物材料而被氧化。 氧化物材料是通道表面上的液体氧化剂和SAM（自组装单层）之一。
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公开(公告)号：KR1020080104860A
公开(公告)日：2008-12-03
申请号：KR1020070052226
申请日：2007-05-29
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/78696 , H01L21/02554 , H01L21/02565 , H01L21/0262 , H01L21/02631 , H01L29/7869
Abstract: A ZnO system thin film transistor and a manufacturing method thereof are provided to improve the electrical characteristic by suppressing the damage caused by the plasma effectively. A ZnO system thin film transistor comprises the substrate(10), the channel layer(22), the gate(20), the gate isolation layer(21), the source and drain electrodes(23a, 23b), and the passivation layer(24). The channel layer is formed on substrate. The channel layer comprises the multi laminated ZnO system unit semiconductor layer. The gate is built between the substrate and the channel layer. The gate isolation layer is prepared between the channel layer and the gate. The source and drain electrodes are prepared at both sides of the channel layer. The passivation layer covers the channel layer, source and drain electrodes. The upper most layer of the channel layer contains the ZnO with the concentration lower than the layer which is under the upper most layer.
Abstract translation: 提供一种ZnO系薄膜晶体管及其制造方法，能够有效地抑制等离子体的损伤来提高电气特性。 ZnO系薄膜晶体管包括衬底（10），沟道层（22），栅极（20），栅极隔离层（21），源极和漏极（23a，23b）和钝化层 24）。 沟道层形成在衬底上。 沟道层包括多层叠ZnO系单位半导体层。 栅极构建在衬底和沟道层之间。 在沟道层和栅极之间制备栅极隔离层。 源极和漏极准备在沟道层的两侧。 钝化层覆盖沟道层，源极和漏极。 沟道层的最上层含有浓度低于最上层的ZnO的ZnO。
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Patent Agency Ranking
公开(公告)号：KR1020080073142A
公开(公告)日：2008-08-08
申请号：KR1020070011794
申请日：2007-02-05
Applicant: 삼성전자주식회사
IPC: H01L21/205
CPC classification number: H01L21/02532 , H01L21/02422 , H01L21/02595 , H01L21/0262
Abstract: A method for manufacturing a polycrystalline silicon thin film is provided to improve throughput of a semiconductor device by forming a large sized polycrystalline silicon thin film on a thermally fragile substrate. A polycrystalline silicon thin film is formed on a substrate(10) by using a vapor deposition process at a vapor atmosphere of a silane source(12) containing silane radicals(14). At a first deposition atmosphere(100), a pressure is at between 22 mT and 100 mT and a silane source amount is adjusted to be 5 sccm and 30 sccm. Silane radicals are guided to collide with each other, such that silicon seed particles(20) are formed on the substrate. At a second deposition atmosphere, a pressure is at between 1 mT and 15 mT and a silane source amount is adjusted to be 1 sccm and 13 sccm. The silicon seed particles are grown on the substrate to form the polycrystalline silicon thin film.
Abstract translation: 提供一种制造多晶硅薄膜的方法，以通过在热脆性基板上形成大尺寸多晶硅薄膜来提高半导体器件的生产能力。 通过在含有硅烷自由基（14）的硅烷源（12）的蒸气气氛下进行气相沉积工艺，在基板（10）上形成多晶硅薄膜。 在第一沉积气氛（100）下，压力在22mT至100mT之间，硅烷源量调整为5sccm和30sccm。 引导硅烷基彼此碰撞，使得硅基颗粒（20）形成在基底上。 在第二沉积气氛下，压力在1mT至15mT之间，硅烷源量调节为1sccm和13sccm。 硅基颗粒在衬底上生长以形成多晶硅薄膜。
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公开(公告)号：KR1020080046508A
公开(公告)日：2008-05-27
申请号：KR1020060116057
申请日：2006-11-22
Applicant: 삼성전자주식회사
CPC classification number: H01L27/1251 , H01L27/1214 , H01L27/1229 , H01L27/3244 , H01L29/04 , H01L29/78696
Abstract: A driving device for an unit pixel of an organic light emitting display and a method for manufacturing the same are provided to improve reliability and production yield by forming each channel of a switching transistor and a driving transistor in one process simultaneously. A driving device for an unit pixel of an organic light emitting display includes a switching transistor(101) and a driving transistor(102) which are coupled to each other. The switching transistor has a first dual channel layer(27a), a first gate electrode(20). The first dual channel has a first amorphous silicon layer(24a) and a first poly-crystal silicon layer(26a) which are sequentially stacked. The first gate electrode is formed on a lower part of the first dual channel layer, and is a counter part of the first amorphous silicon layer. The driving transistor has a second dual channel layer(27b), a second gate electrode(60). The second dual channel has a second amorphous silicon layer(24b) and a second poly-crystal silicon layer(26b) which are sequentially stacked. The second gate electrode is formed on a lower part of the second dual channel layer, and is a counter part of the second amorphous silicon layer.
Abstract translation: 提供有机发光显示器的单位像素的驱动装置及其制造方法，以通过同时在一个处理中形成开关晶体管和驱动晶体管的每个沟道来提高可靠性和生产率。 有机发光显示器的单位像素的驱动装置包括彼此耦合的开关晶体管（101）和驱动晶体管（102）。 开关晶体管具有第一双沟道层（27a），第一栅电极（20）。 第一双通道具有依次层叠的第一非晶硅层（24a）和第一多晶硅层（26a）。 第一栅电极形成在第一双沟道层的下部，并且是第一非晶硅层的对置部分。 驱动晶体管具有第二双沟道层（27b），第二栅电极（60）。 第二双通道具有依次层叠的第二非晶硅层（24b）和第二多晶硅层（26b）。 第二栅电极形成在第二双沟道层的下部，并且是第二非晶硅层的对置部分。
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公开(公告)号：KR1020070110683A
公开(公告)日：2007-11-20
申请号：KR1020060043463
申请日：2006-05-15
Applicant: 삼성전자주식회사
IPC: H01L21/20 , H01L21/205
CPC classification number: H01L21/3221 , H01L21/0237 , H01L21/02532 , H01L21/02667
Abstract: A degassing method of a thin layer and a manufacturing method of a silicon thin film using the same are provided to improve reliability by reducing effectively the amount of impurities within the silicon thin film. A degassing method includes a process for removing residual impurity gas from a thin film(3) formed with a predetermined material by applying microwaves of a predetermined frequency for inducing resonance of gas particles to the thin film, in order to remove the impurity gas from the thin film. The thin film is formed with a silicon thin film. A wavelength of the microwaves has a value of a range of 1mm to 1m. The frequency of the microwave corresponds to a natural frequency of the gas particles. A manufacturing method of the silicon thin film includes a process for forming the silicon thin film on a substrate(1) and a process for removing the residual gas from the silicon thin film by applying the microwaves to the silicon thin film.
Abstract translation: 提供薄层的脱气方法和使用其的硅薄膜的制造方法，以通过有效地减少硅薄膜内的杂质的量来提高可靠性。 脱气方法包括通过施加预定频率的微波来引起气体颗粒与薄膜的共振来从由预定材料形成的薄膜（3）中除去残余杂质气体的方法，以便从 薄膜。 该薄膜由硅薄膜形成。 微波的波长的值为1mm〜1μm的范围。 微波的频率对应于气体颗粒的固有频率。 硅薄膜的制造方法包括在基板（1）上形成硅薄膜的工艺以及通过向硅薄膜施加微波来从硅薄膜除去残留气体的工艺。
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公开(公告)号：KR100612868B1
公开(公告)日：2006-08-14
申请号：KR1020040090495
申请日：2004-11-08
Applicant: 삼성전자주식회사
IPC: H01L21/20 , H01L21/203
CPC classification number: H01L29/66765 , C23C14/3464 , C23C14/46 , H01L21/0242 , H01L21/02422 , H01L21/02532 , H01L21/02631
Abstract: 양질의 다결정 실리콘 TFT의 제조 방법에 관해 개시된다. 본 발명에 따른 다결정 실리콘 TFT의 제조방법은: 기판과 기판에 피착될 실리콘 타겟 물질이 장착된 챔버 내에서, 상기 실리콘 타겟 물질에 이온빔을 조사하는 메인 고주파 유도결합 플라즈마 소스와, 상기 기판에 이온빔을 조사하는 보조 고주파 유도결합 플라즈마 소스를 이용하는 IBD(Ion Beam Deposition)에 의해 250℃의 이하의 온도에서 상기 기판에 실리콘 필름을 형성하는 단계;를 포함한다.
다결정, 바텀, 게이트, TFTAbstract translation: 公开了一种在衬底上制备半导体膜的方法。 该方法包括在沉积室中布置绝缘衬底，并使用离子束沉积将半导体膜沉积到绝缘衬底上，其中沉积期间绝缘衬底的温度不超过250℃。该方法可以产生薄膜晶体管 。 所公开的离子束沉积方法在较低温度和低杂质下形成具有所需光滑度和晶粒尺寸的膜形态。 能够在诸如塑料柔性基底的低熔点基底上沉积半导体膜。
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公开(公告)号：KR100601950B1
公开(公告)日：2006-07-14
申请号：KR1020040024010
申请日：2004-04-08
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/66757 , H01L29/66765 , H01L29/78603 , H01L29/78675 , H01L29/78678
Abstract: 전자소자 및 그 제조방법이 개시된다. 개시된 전자 소자는, 플라스틱 기판과, 상기 기판 상에 적층된 투명한 열전도막과, 상기 열전도막 상에 적층된 폴리 실리콘막과, 상기 폴리 실리콘막 상에 형성된 기능 소자를 구비한다. 상기 기능 소자는, 트랜지스터, 발광소자, 메모리 소자 중 어느 하나이며, 상기 기능 소자는, 상기 폴리 실리콘막 상에 적층된 게이트 적층물을 구비하는 박막 트랜지스터일 수 있다.
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