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1.发明申请CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VERTICAL STIFFNESS CONTROL METHOD 审中-公开电子基板可靠堆叠构造 - 纵向硬度控制方法
公开(公告)号：WO2009092677A2
公开(公告)日：2009-07-30
申请号：PCT/EP2009050524
申请日：2009-01-19
Applicant: IBM , IBM UK , KACKER KARAN , POWELL DOUGLAS OLIVER , QUESTAD DAVID , RUSSELL DAVID JOHN , SRI-JAYANTHA SRI
Inventor： KACKER KARAN , POWELL DOUGLAS OLIVER , QUESTAD DAVID , RUSSELL DAVID JOHN , SRI-JAYANTHA SRI
IPC: H01L23/498
CPC classification number: H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a plated through hole landing supporting the plurality of stacked vias. The plated through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the plated through hole landing.
Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠通孔的电镀通孔着落。 电镀通孔着色包括顺应中心区; 以及用于连接电镀通孔底板的顺应中心区域的弹簧状刚度减小连接器。
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公开(公告)号：BR9000981A
公开(公告)日：1991-02-19
申请号：BR9000981
申请日：1990-03-02
Applicant: IBM
Inventor： DAY RICHARD ALLEN , GELORME JEFFREY DONALD , RUSSELL DAVID JOHN , WITT STEVEN JO
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Patent Agency Ranking
公开(公告)号：MY117343A
公开(公告)日：2004-06-30
申请号：MYPI9601295
申请日：1996-04-05
Applicant: IBM
Inventor： HANSEN JAMES JENS , LAUFFER JOHN MATTHEW , RUSSELL DAVID JOHN
Abstract: A METAL CARRIER (11, 31) HAS A DIELECTRIC MATERIAL (12, 32) WITH A THICKNESS OF LESS THAN 0.1016 MM (0.004 INCH) AND ELECTRICAL VOLTAGE INSULATION CHARACTERISTICS OF AT LEAST 2500 VOLTS FORMED ON A SURFACE. A DONUT CONFIGURED LAND (38) DEFINES AT LEAST ONE VIA (33) OR OPENING FOR REMOVING DIELECTRIC MATERIAL SELECTIVELY. REFLOW SOLDER IS USED TO FORM ELECTRICAL INTERCONNECTIONS (23-28), AND THE VIAS PROVIDE THERMAL DISSIPATION SUFFICIENT TO CONFORM TO SAFETY REQUIREMENTS. (FIGURE 3)
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公开(公告)号：SG70983A1
公开(公告)日：2000-03-21
申请号：SG1996006625
申请日：1996-03-08
Applicant: IBM
Inventor： LAUFFER JOHN MATTHEW , RUSSELL DAVID JOHN , HANSEN JAMES JENS
Abstract: A metal carrier has a dielectric material with a thickness of less than 0.004 inch and electrical voltage insulation characteristics of at least 2500 volts formed on a surface. A donut configured land defines at least one via or opening for removing dielectric material selectively. Reflow solder is used to form electrical interconnections, and the vias provide thermal dissipation sufficient to conform to safety requirements.
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公开(公告)号：DE69013945T2
公开(公告)日：1995-05-24
申请号：DE69013945
申请日：1990-02-01
Applicant: IBM
Inventor： DAY RICHARD ALLEN , GELORME JEFFREY DONALD , RUSSELL DAVID JOHN , WITT STEVEN JO
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公开(公告)号：SG59997A1
公开(公告)日：1999-02-22
申请号：SG1996009698
申请日：1996-05-03
Applicant: IBM
Inventor： KOSTEVA STEPHEN JOHN , PASSANTE DAVID MICHAEL , RUDIK WILLIAM JOHN , RUSSELL DAVID JOHN , WHITCOMB JONATHAN CRAIG
Abstract: A semiconductor package and method for preparing same to obtain improved die adhesion to organic chip carriers has been developed. A copper die bond pad is coated with a passivation material and attached to an organic card with the same passivation material. A semiconductor die may be adhered to the coated die bond pad with either the same passivation material or a common die bond adhesive. Alternatively, the passivation material is coated only on the portion of the die bond pad where the die is attached, and common die bond adhesive attaches the die bond pad to the organic card.
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公开(公告)号：DE69013945D1
公开(公告)日：1994-12-15
申请号：DE69013945
申请日：1990-02-01
Applicant: IBM
Inventor： DAY RICHARD ALLEN , GELORME JEFFREY DONALD , RUSSELL DAVID JOHN , WITT STEVEN JO
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