公开(公告)号：WO2012087548A3

公开(公告)日：2012-08-16

申请号：PCT/US2011063307

申请日：2011-12-05

Applicant: INTEL CORP ,  HUGHES CHRISTOPHER J ,  CHARNEY MARK J ,  CHEN YEN-KUANG ,  CORBAL JESUS ,  FORSYTH ANDREW T ,  GIRKAR MILIND B ,  HALL JONATHAN C ,  IDO HIDEKI ,  VALENTINE ROBERT ,  WIEDEMEIER JEFFREY

Inventor： HUGHES CHRISTOPHER J ,  CHARNEY MARK J ,  CHEN YEN-KUANG ,  CORBAL JESUS ,  FORSYTH ANDREW T ,  GIRKAR MILIND B ,  HALL JONATHAN C ,  IDO HIDEKI ,  VALENTINE ROBERT ,  WIEDEMEIER JEFFREY

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3838

Abstract: A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.

Abstract translation: 描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。 处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。

公开(公告)号：GB2500337A

公开(公告)日：2013-09-18

申请号：GB201311032

申请日：2011-12-05

Applicant: INTEL CORP

Inventor： HUGHES CHRISTOPHER J ,  CHARNEY MARK J ,  CHEN YEN-KUANG ,  FORSYTH ANDREW T ,  GIRKAR MILIND B ,  HALL JONATHAN C ,  IDO HIDEKI ,  VALENTINE ROBERT ,  WIEDEMEIER JEFFREY

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80

Abstract: A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.

公开(公告)号：GB2502936A

公开(公告)日：2013-12-11

申请号：GB201317902

申请日：2011-09-30

Applicant: INTEL CORP

Inventor： VALENTINE ROBERT ,  ADRIAN JESUS CORBAL SAN ,  SANS ROGER ESPASA ,  CAVIN ROBERT D ,  TOLL BRET L ,  DURAN SANTIAGO GALAN ,  WIEDEMEIER JEFFREY ,  SAMUDRALA SRIDHAR ,  GIRKAR MILIND BABURAO ,  GROCHOWSKI EDWARD THOMAS ,  HALL JONATHAN CANNON ,  BRADFORD DENNIS R ,  OULD-AHMED-VALL ELMOUSTAPHA ,  ABEL JAMES C ,  CHARNEY MARK J ,  ABRAHAM SETH ,  SAIR SULEYMAN ,  FORSYTH ANDREW THOMAS ,  YOUNT CHARLES ,  WU LISA K

IPC: G06F15/80 ,  G06F9/30

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.