公开(公告)号：EP3345248A1

公开(公告)日：2018-07-11

申请号：EP16842470.3

申请日：2016-06-22

Applicant: R&D Circuits Inc.

Inventor： WARWICK, Thomas, P. ,  TURPUSEEMA, Dhananjaya ,  RUSSELL, James, V.

IPC: H01R12/00 ,  B33Y80/00 ,  H01R13/02 ,  H05K1/14 ,  H05K3/36 ,  H01L23/522 ,  H01L23/535

CPC classification number: H01R12/52 ,  H01L23/522 ,  H01L23/5225 ,  H01L23/535 ,  H05K1/185 ,  H05K3/4046 ,  H05K2201/09118 ,  H05K2201/10287

Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side

公开(公告)号：EP2225802A2

公开(公告)日：2010-09-08

申请号：EP08863567.7

申请日：2008-12-17

Applicant: R&D Circuits Inc.

Inventor： RUSSELL, James, V.

IPC: H01R12/16 ,  H01R4/58

CPC classification number: H01R13/2414 ,  H01R4/58 ,  H01R13/03 ,  H05K3/245 ,  H05K3/326 ,  H05K2201/0314 ,  H05K2201/10719

Abstract: An electrical connector using an isotropic conductive elastomer as the interconnect medium.

公开(公告)号：EP3304110A1

公开(公告)日：2018-04-11

申请号：EP16803876.8

申请日：2016-02-26

Applicant: R&D Circuits Inc.

Inventor： WARWICK, Thomas, P. ,  RUSSELL, James, V. ,  TURPUSEEMA, Dhananjaya

IPC: G01R31/28

CPC classification number: G01R31/2889 ,  G01R1/07378 ,  G01R31/31901 ,  G01R31/31905

Abstract: The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application, lit each embodiment, however, the critical improvement of this disclosure is the location of the passive components used, for supply filtering/ decoupling relative to prior art. All three embodiments, require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

公开(公告)号：EP2478751A1

公开(公告)日：2012-07-25

申请号：EP10817530.8

申请日：2010-01-08

Applicant: R&D Circuits Inc.

Inventor： RUSSELL, James, V.

IPC: H05K1/18 ,  H01L23/32 ,  H05K3/30

CPC classification number: H05K3/30 ,  G01R1/07378 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/13 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/14 ,  H05K1/0213 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/141 ,  H05K1/185 ,  H05K2201/049 ,  H05K2201/10378 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Embedding a power modification component such as a capacitance inside of an adaptor board located to extend over and beyond the vias of the main circuit board so that a portion of the interposer board containing the embedded capacitance is located beyond where the vias or blinds are located. This permits that via to conduct through the opening. In this way, the capacitance and the resistance will have a closer contact point to the electrical component. A resistance can also be embedded in an opening in the adaptor board and be vertically aligned within the opening to make contact with a pad on top of the adaptor board and a pad at the bottom of the adaptor board so that electricity conducts through the embedded component.

公开(公告)号：EP2798702A1

公开(公告)日：2014-11-05

申请号：EP13777883.3

申请日：2013-03-28

Applicant: R&D Circuits Inc.

Inventor： WARWICK, Thomas, P. ,  RUSSELL, James, V. ,  MCMULLIN, Dermick ,  QUICK, William

IPC: H01R12/00

CPC classification number: H01R13/03 ,  H01R12/52 ,  H01R13/2414 ,  H01R43/26 ,  Y10T29/49208 ,  Y10T29/4921

Abstract: A method and an electrical interconnect mechanism in which elastomeric pins are printed onto metal retainer tabs having at least one protrusion or tab extending laterally therefrom to engage a catch or recess of the laminated housing so as to locate each of the elastomeric pins and secure them within the housing. In one embodiment a champher may be employed with a catch or recess to engagely secure a second protrusion or tab extending laterally from another side of said elastomeric pin. In another embodiment the elastomeric pin may have a solid metal ring or a slide collar around the center of the pin wherein the ring has one or two tabs for engaging the recess in the housing and if preferred also the recess of a champfer.

公开(公告)号：EP2428105A1

公开(公告)日：2012-03-14

申请号：EP10772351.2

申请日：2010-01-08

Applicant: R&D Circuits Inc.

Inventor： RUSSELL, James, V.

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H05K1/185 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/112 ,  H05K3/4046 ,  H05K2201/096 ,  H05K2201/10636 ,  Y02P70/611

Abstract: The present disclosure relates to embedding a power modification component such as a capacitance or a resistance inside of pads that are located to extend over and beyond the vias of the PCB so that a portion of the pad containing the embedded capacitance or resistance is located beyond where the vias or blinds are located. Each of the pads will include an opening that is located over a given one of the vias or blinds to permit that via to conduct through the opening. In this way the capacitance and the resistance will have a closer contact point the electrical component.

公开(公告)号：WO2016195766A1

公开(公告)日：2016-12-08

申请号：PCT/US2016/019865

申请日：2016-02-26

Applicant: R&D CIRCUITS, INC.

Inventor： WARWICK, Thomas, P. ,  RUSSELL, James, V. ,  TURPUSEEMA, Dhananjaya

IPC: G01R31/28

CPC classification number: G01R31/2889 ,  G01R1/07378 ,  G01R31/31901 ,  G01R31/31905

Abstract: The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application, lit each embodiment, however, the critical improvement of this disclosure is the location of the passive components used, for supply filtering/ decoupling relative to prior art. All three embodiments, require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

Abstract translation: 本发明基本上描述了实现针对芯片的低阻抗（过频）功率传递的三个不同实施例。 这种低阻抗到高频允许管芯以封装级速度工作，从而降低封装级别的产量损失。 每个实施例解决了每个实施例的整个晶片探针应用的略微不同的方面，然而，本公开的关键改进是所使用的无源部件的位置，用于相对于现有技术的电源滤波/去耦。 所有三个实施例都需要一种方法来将无源部件嵌入到靠近螺距平移基板的位置，或物理地嵌入螺距平移基板。

公开(公告)号：WO2009082461A2

公开(公告)日：2009-07-02

申请号：PCT/US2008/013842

申请日：2008-12-17

Applicant: R & D CIRCUITS INC.

Inventor： RUSSELL, James, V.

IPC: H01R12/16 ,  H01R4/58

CPC classification number: H01R13/2414 ,  H01R4/58 ,  H01R13/03 ,  H05K3/245 ,  H05K3/326 ,  H05K2201/0314 ,  H05K2201/10719

Abstract: An electrical connector using an isotropic conductive elastomer as the interconnect medium.

Abstract translation:

一种使用各向同性导电弹性体作为互连介质的电连接器。

公开(公告)号：WO2015168370A1

公开(公告)日：2015-11-05

申请号：PCT/US2015/028453

申请日：2015-04-30

Applicant: R&D CIRCUITS, INC

Inventor： TURPUSEEMA, Dhanonjaya ,  WARWICK, Thomas, P. ,  SMITH, Thomas ,  RUSSELL, James, V.

IPC: H05K3/30 ,  H05K3/46 ,  H05K3/40 ,  G06K19/077 ,  H05K1/18

CPC classification number: H05K1/188 ,  H05K1/144 ,  H05K1/183 ,  H05K1/186 ,  H05K3/0026 ,  H05K3/0094 ,  H05K3/321 ,  H05K3/366 ,  H05K3/4655 ,  H05K3/4679 ,  H05K2201/032 ,  H05K2201/0355 ,  H05K2201/042 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09545 ,  H05K2201/09572 ,  H05K2203/0485 ,  H05K2203/063 ,  H05K2203/11 ,  Y10T29/49128 ,  Y10T29/4914

Abstract: A method and electrical interconnect structure internal to a printed circuit board for the purposes of creating a reliable, high performing connection method between embedded component terminals, signal traces and or power/ground planes which may occupy the same vertical space as the embedded components, such as a capacitor or resistor. Further easing the assembly and reliability through the manufacturing process of said embedded component structures. In one structure castellated drilled, plated vias connect the trace or plane within the printed circuit board to the electrical terminals of the embedded component using a permanent and highly conductive attach material. In another structure, the trace or plane connect by selective side-wall plating, which surrounds the electrical terminal of the component This structure also uses a permanent and highly conductive attach material to electrically connect the component terminal to the plated side-wall and in a final embodiment the terminals are connected through a conductive attach material through a via in the z axis to a conductive pad.

Abstract translation: 印刷电路板内部的方法和电互连结构，用于在嵌入式组件端子，信号迹线和/或电源/接地平面之间建立可靠的，高性能的连接方法，其可能占据与嵌入式组件相同的垂直空间，例如 作为电容器或电阻器。 通过所述嵌入式组件结构的制造过程进一步减轻组装和可靠性。 在一种结构化的钻孔中，电镀通孔使用永久且高度导电的附着材料将印刷电路板中的迹线或平面连接到嵌入式部件的电气端子。 在另一种结构中，轨迹或平面通过选择性侧壁电镀连接，其围绕部件的电端子。该结构还使用永久且高度导电的附着材料将部件端子电连接到电镀侧壁 最终实施例中，端子通过导电附着材料通过z轴中的通孔连接到导电垫。

公开(公告)号：WO2012047266A3

公开(公告)日：2012-04-12

申请号：PCT/US2011/001663

申请日：2011-09-28

Applicant: R&D CIRCUITS, INC.

Inventor： WARWICK, Thomas, P. ,  RUSSELL, James, V.

IPC: H01P1/20 ,  H01P1/203 ,  H01P1/205

Abstract: The present disclosure relates to reducing unwanted RF noise in a printed circuit board (PCB) containing an RF device. An isolation filter is embedded in a PCB containing an RDF device. By placing the isolation filter as close as possible to the RF device in order to dramatically reduce unwanted RF noise due to unavoidable coupling between Vias and planes in the PCB structure.