公开(公告)号：US20240074035A1

公开(公告)日：2024-02-29

申请号：US18029023

申请日：2021-09-28

Applicant: KYOCERA Corporation

Inventor： Yoshiki KAWAZU ,  Taito KIMURA

IPC: H05K1/02 ,  H01P3/08

CPC classification number: H05K1/0219 ,  H01P3/081 ,  H05K2201/09227 ,  H05K2201/09609 ,  H05K2201/09672 ,  H05K2201/0969

Abstract: A wiring base includes a base, a signal conductor, and a ground conductor including a first ground conductor. The base includes a first surface, a first region, and a second region. The first region is located near an outer side of the first surface. An external board is mounted in the first region. The second region is other than the first region. The signal conductor extends through a region including the first region of the first surface in a first direction away from the outer side. The first ground conductor is located in the base at a distance from the signal conductor of less than ¼ of a wavelength of a high-frequency signal. The high-frequency signal is transmitted through the signal conductor. The first ground conductor includes a first grid portion at a first location overlapping the first region and at least a portion of the signal conductor.

公开(公告)号：US11647581B2

公开(公告)日：2023-05-09

申请号：US16903694

申请日：2020-06-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuki Takemori

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/28 ,  B32B3/26 ,  B32B15/04 ,  B32B3/30 ,  B32B9/00 ,  B32B9/04 ,  H05K1/02 ,  H05K3/34 ,  H05K3/46 ,  H05K3/24

CPC classification number: H05K1/0306 ,  B32B3/263 ,  B32B3/266 ,  B32B3/30 ,  B32B9/005 ,  B32B9/043 ,  B32B15/04 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/285 ,  H05K3/34 ,  H05K3/4644 ,  H05K3/244 ,  H05K2201/017 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2201/099 ,  H05K2201/0969 ,  H05K2201/09145 ,  H05K2201/09436 ,  H05K2201/09481 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2203/1131 ,  Y10T428/12201 ,  Y10T428/12361 ,  Y10T428/24273 ,  Y10T428/24331

Abstract: A ceramic electronic component that includes an electronic component body having a superficial base ceramic layer; a surface electrode on a surface of the electronic component body, a peripheral section of the surface electrode having an opening therein; and a covering ceramic layer covering the peripheral section of the surface electrode and the opening therein.

公开(公告)号：US09974165B2

公开(公告)日：2018-05-15

申请号：US15418918

申请日：2017-01-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Naoki Gouchi

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/02 ,  H05K3/40 ,  H05K3/24

CPC classification number: H05K1/0287 ,  H05K1/0292 ,  H05K1/0293 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/0393 ,  H05K1/111 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/24 ,  H05K3/4007 ,  H05K3/4092 ,  H05K3/4632 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10007 ,  H05K2201/10159 ,  H05K2201/10984 ,  H05K2201/2072 ,  H05K2203/0271 ,  H05K2203/063 ,  H05K2203/08

Abstract: To prevent decrease of the bonding strength of an electronic component and a multilayer substrate, an electronic component-embedded module may include an electronic component having a plurality of pads and a multilayer substrate which includes a plurality of resin layers and a cavity for containing the electronic component. The multilayer substrate may include a first resin layer having a plurality of first pattern conductors and a space, and a second resin layer having a second pattern conductor and a plurality of third pattern conductors. The plurality of third pattern conductors may be in conduction with either of the first pattern conductors or the pads, with the second resin layer being placed over the first resin layer. The second pattern conductor may be arranged around a first pad with a gap, and the second resin layer is present between the second pattern conductor and at least one of the first pads.

公开(公告)号：US09888583B2

公开(公告)日：2018-02-06

申请号：US14815413

申请日：2015-07-31

Applicant: MINEBEA CO., LTD.

Inventor： Dohaku Inamori ,  Takashi Kashino

IPC: H05K1/00 ,  H05K3/36 ,  H05K1/14 ,  H05K1/11

CPC classification number: H05K1/118 ,  H05K1/0393 ,  H05K1/113 ,  H05K1/116 ,  H05K1/147 ,  H05K3/363 ,  H05K2201/09036 ,  H05K2201/0969 ,  H05K2201/09745 ,  H05K2203/1178

Abstract: There is provided a flexible printed circuit board. The flexible printed circuit board includes: a flexible insulation layer having a first surface and a second surface; a first land which is conductive and which is provided on the first surface of the flexible insulation layer; and a conductive member which is provided on the second surface of the flexible insulation layer. A recess is formed on the first land.

公开(公告)号：US09882256B2

公开(公告)日：2018-01-30

申请号：US15156395

申请日：2016-05-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru Kato ,  Shigeru Tago ,  Jun Sasaki ,  Junichi Kurita ,  Satoshi Sasaki

IPC: H01P3/08 ,  H01P3/02 ,  H04B15/00 ,  H01P3/10 ,  H03H7/38 ,  H01P3/12 ,  H01P3/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H01P1/203

CPC classification number: H01P3/085 ,  H01L2224/16225 ,  H01L2924/19105 ,  H01P1/20363 ,  H01P3/003 ,  H01P3/026 ,  H01P3/08 ,  H01P3/10 ,  H01P3/121 ,  H03H7/38 ,  H04B15/00 ,  H05K1/0219 ,  H05K1/0225 ,  H05K1/0242 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/028 ,  H05K1/0393 ,  H05K1/113 ,  H05K2201/09618 ,  H05K2201/0969 ,  H05K2201/09727

Abstract: An easily bendable high-frequency signal transmission line includes a dielectric body including a protection layer and dielectric sheets laminated on each other, a surface and an undersurface. A signal line is a linear conductor disposed in the dielectric body. A ground conductor is disposed in the dielectric body, faces the signal line via the dielectric sheet, and continuously extends along the signal line. A ground conductor is disposed in the dielectric body, faces the ground conductor via the signal line sandwiched therebetween, and includes a plurality of openings arranged along the signal line. The surface of the dielectric body on the side of the ground conductor with respect to the signal line is in contact with a battery pack.

公开(公告)号：US09875823B2

公开(公告)日：2018-01-23

申请号：US14494994

申请日：2014-09-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Satoshi Sasaki

IPC: H05K1/00 ,  H01B7/08 ,  H01P3/08 ,  H01B3/30 ,  H05K1/02

CPC classification number: H01B7/0823 ,  H01B3/306 ,  H01P3/085 ,  H05K1/0221 ,  H05K1/0225 ,  H05K1/0253 ,  H05K1/028 ,  H05K2201/055 ,  H05K2201/09618 ,  H05K2201/0969

Abstract: A flat cable includes a dielectric element assembly including a plurality of dielectric layers laminated on each other in a direction of lamination, and a linear signal line provided in the dielectric element assembly. The dielectric element assembly includes at least one section bent in a plurality of places defining a zigzag shape when viewed in a plan view in the direction of lamination. In the zigzag section of the dielectric element assembly, any portions of the dielectric element assembly that are not adjacent across a bending line do not overlap when viewed in a plan view in the direction of lamination.

公开(公告)号：US20170271288A1

公开(公告)日：2017-09-21

申请号：US15611812

申请日：2017-06-02

Applicant: GE Embedded Electronics Oy

Inventor： Antti Iihola ,  Risto Tuominen

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H05K1/18 ,  H05K3/30

CPC classification number: H01L24/09 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/188 ,  H05K3/305 ,  H05K2201/0969 ,  H05K2201/10674 ,  H01L2924/00

Abstract: Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern.

公开(公告)号：US09691724B2

公开(公告)日：2017-06-27

申请号：US14161735

申请日：2014-01-23

Applicant: GE Embedded Electronics Oy

Inventor： Antti Iihola ,  Risto Tuominen

IPC: H01L23/02 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H05K1/18 ,  H01L25/065 ,  H05K3/30

CPC classification number: H01L24/09 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/188 ,  H05K3/305 ,  H05K2201/0969 ,  H05K2201/10674 ,  H01L2924/00

Abstract: Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern.

公开(公告)号：US09681550B2

公开(公告)日：2017-06-13

申请号：US12200749

申请日：2008-08-28

Applicant: Joseph C. Fjelstad

Inventor： Joseph C. Fjelstad

IPC: H05K1/18 ,  H05K1/05 ,  H05K3/28 ,  H05K3/46

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/92144 ,  H01L2224/96 ,  H01L2924/14 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/056 ,  H05K3/284 ,  H05K3/4644 ,  H05K2201/0969 ,  H05K2201/2018 ,  H05K2203/0156 ,  H05K2203/1469 ,  Y10T29/49124 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A frame 100 containing aperture(s) 102, 103, 104 is positioned on and joined to a permanent substrate 206a or temporary substrate 206b. Electrical component(s) 202, 203, 204 are placed into respective aperture(s) 102, 103, 104 with the leads 504, 1002 of the component(s) 202, 203, 204 positioned on and attached to the permanent substrate 206a or the temporary substrate 206b. Then an encapsulant 402, electrically insulating, but preferably thermally conductive, envelops the component(s) 102, 103, 104. At this point, temporary substrate 206b may be removed exposing component leads 1002. Or, if component(s) 102, 103, 104 are mounted on permanent substrate 206a, vias 502 extend from the surface of substrate 206a to leads 504. With leads 504, 1002 exposed, the completed subassembly 500, 1000 may be incorporated into various forms of reverse-interconnection process (RIP) assemblies as detailed in related applications.

公开(公告)号：US09668346B2

公开(公告)日：2017-05-30

申请号：US14037645

申请日：2013-09-26

Applicant: Mitsubishi Electric Corporation

Inventor： Mizuki Shirao ,  Nobuo Ohata ,  Nobuyuki Yasui ,  Hiroshi Aruga

IPC: H05K1/11 ,  H01P3/00 ,  H01P3/08 ,  H01P5/02 ,  H05K1/02 ,  H05K3/36

CPC classification number: H05K1/118 ,  H01P3/003 ,  H01P3/081 ,  H01P5/028 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0253 ,  H05K3/363 ,  H05K2201/09181 ,  H05K2201/09481 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/0969 ,  H05K2201/09727

Abstract: A terminal portion configured to obtain electrical connection with a printed circuit board includes a first signal pad that is formed in a first conductor layer and is electrically separated from a ground layer, a pair of first ground pads that is formed in the first conductor layer to sandwich the first signal pad and is connected to the ground layer, a second signal pad that is formed in a second conductor layer and is connected to a signal line, a pair of second ground pads that is formed in the second conductor layer to sandwich the second signal pad and is electrically separated from the signal line, a third signal pad formed in a third conductor layer, and a pair of third ground pads formed in the third conductor layer to sandwich the third signal pad. The second signal pad is wider than the third signal pad.