公开(公告)号：US09814129B2

公开(公告)日：2017-11-07

申请号：US15184511

申请日：2016-06-16

Applicant: LG INNOTEK CO., LTD.

Inventor： Yong Seok Cho ,  Chang Sung Kim

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K3/28

CPC classification number: H05K1/0203 ,  H05K1/0209 ,  H05K1/0227 ,  H05K1/09 ,  H05K3/28 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09227 ,  H05K2201/09881

Abstract: Disclosed is a printed circuit board. The printed circuit board includes an insulating layer, a copper foil formed on the insulating layer and formed therein with a groove to expose a portion of a top surface of the insulating layer, and a thermal conductive layer filled in the groove.

公开(公告)号：US09420703B2

公开(公告)日：2016-08-16

申请号：US14237065

申请日：2013-05-27

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Takahiro Hayashi ,  Makoto Nagai ,  Tatsuya Ito ,  Seiji Mori ,  Makoto Wakazono ,  Tomohiro Nishida

IPC: H05K1/00 ,  H05K3/40 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H05K3/34 ,  H05K1/02 ,  H05K1/03 ,  H05K3/46 ,  H05K3/28

CPC classification number: H05K3/4007 ,  H01L21/4846 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/81 ,  H01L2224/10175 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/8114 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K1/0298 ,  H05K1/0366 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/4661 ,  H05K3/4688 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2201/10674 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: To provide a wiring board in which wiring conductors are securely protected by a precise and rigid dam portion formed on an outermost layer of a laminate and that is excellent in connection reliability with a semiconductor chip. A laminate that configures this wiring board includes multiple connection terminal portions and wiring conductors as a conductor layer of the outermost layer. The wiring conductors are arranged at predetermined positions, passing through between multiple connection terminal portions for flip-chip mounting a semiconductor chip. A resin insulating layer of the outermost layer of the laminate has a dam portion and a reinforcement portion. The dam portion covers the wiring conductors. The reinforcement portion is formed, between the wiring conductor and the connection terminal portion that is adjacent to the wiring conductor, lower than a height of the dam portion. The reinforcement portion is concatenated with a side surface of the dam portion.

Abstract translation: 为了提供布线基板，其中布线导体被形成在层压体的最外层上的精确且刚性的坝部可靠地保护，并且与半导体芯片的连接可靠性优异。 构成该布线基板的层叠体具有作为最外层的导体层的多个连接端子部和布线导体。 布线导体布置在预定位置，通过多个连接端子部分之间用于倒装芯片安装半导体芯片。 层叠体的最外层的树脂绝缘层具有阻挡部和加强部。 大坝部分覆盖布线导体。 加强部分形成在布线导体和与布线导体相邻的连接端子部分之间，比坝部的高度低。 加强部分与坝部分的侧表面连接。

公开(公告)号：US20150305150A1

公开(公告)日：2015-10-22

申请号：US14754796

申请日：2015-06-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroyuki OHATA

IPC: H05K1/03 ,  B32B37/06 ,  B32B37/10

CPC classification number: H05K1/0353 ,  B32B37/04 ,  B32B37/06 ,  B32B37/10 ,  B32B38/145 ,  B32B2305/55 ,  B32B2457/202 ,  C08J3/28 ,  C08J2300/00 ,  C08J2367/00 ,  C09K19/38 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/09881 ,  H05K2201/09909

Abstract: A multi-layer resin substrate is a multi-layer resin substrate integrated by stacking and thermocompression bonding a plurality of resin layers each composed of a thermoplastic resin as a main material and having a main surface. The plurality of resin layers include a resin layer having a pattern member arranged on the main surface. A surface of at least some resin layers of the plurality of resin layers has a paint layer, which is obtained by applying a thermoplastic resin paint to a region corresponding to a region insufficient in thickness as a stack as a whole during a process for stacking and thermocompression bonding the plurality of resin layers. The pattern member is provided, for example, by a conductor pattern.

Abstract translation: 多层树脂基板是通过以热塑性树脂作为主要材料并且具有主表面的多个树脂层堆叠并热压接合而成的多层树脂基板。 多个树脂层包括具有布置在主表面上的图案构件的树脂层。 多个树脂层的至少一些树脂层的表面具有涂料层，其通过在堆叠过程中将热塑性树脂涂料作为整体施加热塑性树脂涂料作为整体的厚度不足的区域， 热压接合多个树脂层。 图案构件例如由导体图案提供。

公开(公告)号：US09003653B2

公开(公告)日：2015-04-14

申请号：US12594183

申请日：2008-02-07

Applicant: Juergen Egerter ,  Walter Roethlingshoefer ,  Markus Werner

Inventor： Juergen Egerter ,  Walter Roethlingshoefer ,  Markus Werner

IPC: H01K3/22 ,  H01L21/48 ,  H05K3/46 ,  H05K1/03

CPC classification number: H01L21/4807 ,  H01L21/4857 ,  H05K1/0306 ,  H05K3/465 ,  H05K3/4667 ,  H05K2201/09881 ,  H05K2203/0169 ,  H05K2203/1344 ,  H05K2203/1366 ,  Y10T29/49126 ,  Y10T29/4916 ,  Y10T29/49163

Abstract: A method for producing a ceramic multilayer circuit system, and a corresponding multilayer circuit system are provided. An embodiment of the method includes sequential deposition of a plurality of circuit layers of the multilayer circuit system on a substrate using a powder spray method; pressing of the deposited plurality of circuit layers; and thermal sintering of the pressed plurality of circuit layers. The individual circuit layers have electrically conductive areas made of at least one conductive material and electrically insulating areas made of at least one ceramic material.

Abstract translation: 提供一种陶瓷多层电路系统的制造方法以及相应的多层电路系统。 该方法的实施例包括使用粉末喷涂方法将多层电路系统的多个电路层顺次沉积在基板上; 压制沉积的多个电路层; 和压制的多个电路层的热烧结。 单个电路层具有由至少一种导电材料制成的导电区域和由至少一种陶瓷材料制成的电绝缘区域。

公开(公告)号：US20140353018A1

公开(公告)日：2014-12-04

申请号：US14287242

申请日：2014-05-27

Applicant: HITACHI, LTD.

Inventor： Akira SOEDA ,  Chiko YORITA ,  Shinichirou TOOYA ,  Takayuki ONO ,  Mitsuru TAKAHIRA ,  Yuuichi SEKINO ,  Akira GOTO ,  Yoshimasa TASHIRO ,  Hiroyuki DOI ,  Tsutomu SAKAMOTO

IPC: H05K3/40 ,  H05K1/09 ,  H05K1/11 ,  H05K1/03

CPC classification number: H05K3/4614 ,  H05K1/113 ,  H05K1/114 ,  H05K3/0094 ,  H05K3/306 ,  H05K2201/044 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2201/099 ,  H05K2201/10189 ,  H05K2201/10234 ,  H05K2203/061 ,  H05K2203/063 ,  Y10T29/49165

Abstract: An electrode connected to a TH pad requiring electric conduction is formed on a bonded surface of a first multilayer substrate having piercing TH to form a solder bump on the electrode. An electrode connected to the TH pad is formed on a bonded surface of a second multilayer substrate to be bonded having a piercing TH at a position opposite the electrode formed on the first multilayer substrate to form a solder bump on the electrode. A three-layered sheet is formed by applying an adhesive as a resin material that is not completely cured to both surfaces of a core material as the cured resin, and has holes at positions corresponding to the TH and the solder bump, respectively. The first and the second multilayer substrates are then laminated having the bonded surfaces facing each other while having the three-layered sheet positioned and interposed therebetween, and batch thermocompression bonded.

Abstract translation: 在具有穿刺TH的第一多层基板的接合表面上形成连接到需要导电的TH垫的电极，以在电极上形成焊料凸块。 连接到TH焊盘的电极形成在与要形成在第一多层基板上的电极相对的位置处具有穿刺TH的待接合的第二多层基板的接合表面上，以在电极上形成焊料凸块。 通过将作为树脂材料的粘合剂施加到作为固化树脂的芯材的两个表面的树脂材料上，并且在与TH和焊料凸块相对应的位置处分别具有孔，形成三层片。 然后将第一和第二多层基板层压，其中具有彼此面对的接合表面，同时具有定位并插入其中的三层片材，并进行批量热压接。

公开(公告)号：US08745863B2

公开(公告)日：2014-06-10

申请号：US13169674

申请日：2011-06-27

Applicant: Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

IPC: H01K3/10

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A method of manufacturing a multi-layer printed circuit board includes the following steps (A) and (B). (A) Providing penetrating openings which are formed into through holes and each of which has a small diameter for a core substrate, and (B) providing penetrating openings which are formed into through holes each having a large diameter for the core substrate.

Abstract translation: 制造多层印刷电路板的方法包括以下步骤（A）和（B）。 （A）提供穿透开口，其形成为通孔，并且每个具有用于芯基板的小直径，以及（B）提供形成为具有用于芯基板的大直径的通孔的穿透开口。

公开(公告)号：US20140131076A1

公开(公告)日：2014-05-15

申请号：US14128954

申请日：2012-12-21

Applicant: PANASONIC CORPORATION

Inventor： Taiji Kuroiwa ,  Seiichi Nakatani ,  Yoshihisa Yamashita ,  Susumu Sawada

IPC: H05K3/22 ,  H05K1/03

CPC classification number: H05K3/22 ,  H05K1/0306 ,  H05K3/4007 ,  H05K3/4629 ,  H05K2201/017 ,  H05K2201/09481 ,  H05K2201/09881 ,  H05K2203/0139 ,  Y10T29/49155

Abstract: In the present invention, a ceramic substrate composite comprising, on a ceramic substrate, a conductor pattern composite and an insulating layer is provided. The ceramic substrate composite of the present invention is characterized in that the conductor pattern composite and the insulating layer are provided on the ceramic substrate with each other so that the insulating layer overlaps a part of the conductor pattern composite; and wherein the conductor pattern composite is composed of a conductor portion and an insulating portion that exists locally in the conductor portion, the insulating portion being an insulating material that constitutes the insulating layer.

Abstract translation: 在本发明中，提供一种在陶瓷基板上包含导体图案复合体和绝缘层的陶瓷基板复合体。 本发明的陶瓷基板复合体的特征在于，导体图案复合体和绝缘层设置在陶瓷基板上，使得绝缘层与导体图案复合体的一部分重叠; 并且其中所述导体图案复合体由导体部分和局部存在于所述导体部分中的绝缘部分构成，所述绝缘部分是构成所述绝缘层的绝缘材料。

公开(公告)号：US20140097007A1

公开(公告)日：2014-04-10

申请号：US14037496

申请日：2013-09-26

Applicant: NGK Spark Plug Co., Ltd.

Inventor： Makoto NAGAI ,  Seiji MORI ,  Takahiro HAYASHI ,  Tatsuya ITO

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0265 ,  H05K3/00 ,  H05K3/3452 ,  H05K3/3484 ,  H05K3/4007 ,  H05K2201/09881 ,  H05K2203/0574

Abstract: Embodiments of the present wiring substrate include a stacked body including one or more insulation layers and one or more conductive layers, wherein the wiring substrate has a plurality of connection terminals formed on the stacked body, each connection terminal has a top surface whose area is smaller than that of each of opposite side surfaces thereof, and a filling member provided in a filling manner between the connection terminals. The top surface of each connection terminal has an area larger than that of a portion of each side surfaces portion exposed from the filling member, and a bonding layer containing a solder is formed on the top surface.

Abstract translation: 本发明的布线基板的具体实施方式包括具有一个以上的绝缘层和一个以上的导电层的层叠体，其中，布线基板具有形成在层叠体上的多个连接端子，各连接端子的面积较小的顶面 比其各个相对侧面的填充构件和填充构件设置在连接端子之间。 每个连接端子的顶表面的面积大于从填充构件露出的每个侧表面部分的部分的面积，并且在顶表面上形成包含焊料的接合层。

公开(公告)号：US08667675B2

公开(公告)日：2014-03-11

申请号：US12190551

申请日：2008-08-12

Applicant: George Dudnikov, Jr.

Inventor： George Dudnikov, Jr.

IPC: H01K3/10

CPC classification number: H05K3/429 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/116 ,  H05K1/167 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/0187 ,  H05K2201/0738 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09718 ,  H05K2201/09881 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

Abstract translation: 公开了通过在PCB堆叠中使用电镀抗蚀剂将多个通孔结构同时分隔成电隔离部分的系统和方法。 通过在子复合结构中的一个或多个位置选择性地沉积电镀抗蚀剂来制造这种通孔结构。 具有在不同位置沉积的电镀抗蚀剂的多个亚复合结构层压以形成期望的PCB设计的PCB堆叠。 通过PCB堆叠穿过导电层，电介质层和通过电镀抗蚀剂钻穿孔。 因此，PCB面板具有多个通孔，然后可以通过将PCB面板放置在种子池中，然后浸入无电镀铜浴中而同时进行电镀。 这种分隔的通孔增加布线密度并限制通孔结构中的短截线形成。 这种分隔的通孔允许多个电信号穿过每个电隔离部分而没有彼此的干扰。

公开(公告)号：US08625248B2

公开(公告)日：2014-01-07

申请号：US13123262

申请日：2009-10-06

Applicant: Mina Onishi ,  Yoshimitsu Ishihara ,  Hirofumi Inoue ,  Yukihiko Azuma

Inventor： Mina Onishi ,  Yoshimitsu Ishihara ,  Hirofumi Inoue ,  Yukihiko Azuma

IPC: H02H1/04 ,  H02H3/22

CPC classification number: H01C7/12 ,  H01T4/10 ,  H05K1/0259 ,  H05K2201/09672 ,  H05K2201/09881

Abstract: The present invention provides an electrostatic discharge protector capable of protecting electronic circuit boards having various designs from electrostatic discharge freely, simply and easily. The electrostatic discharge protector of the present invention comprises at least three conductive members containing one pair of electrodes and the conductive members other than the electrodes, the conductive members are each disposed in such a way that the gap between one conductive member and the other conductive member has a width of 0.1 to 10 μm, an insulating member is disposed and embedded in at least one of gaps having a width of 0.1 to 10 μm which are adjacent to each conductive member and one electrode is connected to the other electrode paired with the one electrode through the insulating member and the conductive members other than electrodes.

Abstract translation: 本发明提供一种静电放电保护器，其能够简单且容易地保护具有各种设计的电子电路板免受静电放电。 本发明的静电放电保护器包括至少三个包含一对电极的导电构件和除电极之外的导电构件，导电构件各自设置成使得一个导电构件和另一个导电构件之间的间隙 具有0.1至10微米的宽度，绝缘构件设置并嵌入在与每个导电构件相邻的宽度为0.1至10μm的间隙中的至少一个中，并且一个电极连接到与该一个配对的另一个电极 电极通过绝缘构件和除电极之外的导电构件。