公开(公告)号：US20090166833A1

公开(公告)日：2009-07-02

申请号：US12061914

申请日：2008-04-03

Applicant: STEVEN WEBSTER ,  YING-CHENG WU ,  MENG-LUNG YU ,  SHIH-MIN LO

Inventor： STEVEN WEBSTER ,  YING-CHENG WU ,  MENG-LUNG YU ,  SHIH-MIN LO

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H01L25/50 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/107 ,  H05K1/0284 ,  H05K1/119 ,  H05K1/183 ,  H05K3/0052 ,  H05K2201/10545 ,  H05K2201/10734

Abstract: A semiconductor unit includes an interface plate, a supporting plate integrally formed with the interface plate, two chip packages positioned at opposite sides of the supporting plate, and leading traces running in the interface plate and the supporting plate, connected with the chip packages respectively.

Abstract translation: 半导体单元包括接口板，与接口板一体形成的支撑板，位于支撑板的相对侧的两个芯片封装，以及分别与芯片封装相连接的界面板和支撑板中的导线。

公开(公告)号：US20090152742A1

公开(公告)日：2009-06-18

申请号：US12213796

申请日：2008-06-24

Applicant: Nobuyuki Ikeguchi ,  Keungjin Sohn ,  JoonSik Shin ,  Jung-Hwan Park

Inventor： Nobuyuki Ikeguchi ,  Keungjin Sohn ,  JoonSik Shin ,  Jung-Hwan Park

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H05K1/144 ,  H01L23/13 ,  H01L23/145 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H05K1/0366 ,  H05K1/056 ,  H05K1/182 ,  H05K3/4608 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10674

Abstract: A method of manufacturing a semiconductor package may include: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs.

Abstract translation: 制造半导体封装的方法可以包括：形成第一板; 在其中形成有至少一个空腔的第二板; 将第二板连接到第一板的两侧，使得第二板与第一板电连接; 以及通过将所述部件嵌入所述空腔中，通过倒装芯片方法将至少一个部件与所述第一板连接。 该方法可以防止对半导体芯片的损坏并降低制造成本，同时连接材料还可以减轻应力，防止板和半导体芯片中的开裂，同时​​防止诸如弯曲和翘曲的缺陷。 也可以避免温度变化引起的缺陷。 此外，不需要在半导体芯片与印刷电路板连接的部分中使用底部填充，这允许更容易的返工和降低成本。

公开(公告)号：US20090121326A1

公开(公告)日：2009-05-14

申请号：US11953967

申请日：2007-12-11

Applicant: Jong Hoon KIM ,  Min Suk SUH ,  Seong Cheol KIM ,  Seung Taek YANG ,  Seung Hyun LEE

Inventor： Jong Hoon KIM ,  Min Suk SUH ,  Seong Cheol KIM ,  Seung Taek YANG ,  Seung Hyun LEE

IPC: H01L23/495 ,  H01L23/538

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H05K1/021 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0061 ,  H05K2201/10371 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/1572

Abstract: A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module.

Abstract translation: 一种半导体封装模块，包括：电路板，包括具有接收部分的基板主体和形成在所述基板主体上的导电图案; 接收在所述接收部分中并且具有电连接到所述导电图案的导电端子和与所述导电端子电连接的半导体芯片的半导体封装; 以及电连接导电图案和导电端子的连接构件。 在本发明中，在电路基板的基板主体中形成具有接收空间的接收部分，并且在接收部分中接收半导体封装的接收部分，以及半导体封装的连接端子和板体的导电图案 使用连接构件电连接，多个半导体封装可以堆叠在单个电路板中而不增加厚度，从而显着提高半导体封装模块的数据存储容量和数据处理速度。

公开(公告)号：US07466560B2

公开(公告)日：2008-12-16

申请号：US11219114

申请日：2005-09-02

Applicant: Seiji Hayashi ,  Hideho Inagawa

Inventor： Seiji Hayashi ,  Hideho Inagawa

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0231 ,  H05K1/165 ,  H05K3/429 ,  H05K2201/09263 ,  H05K2201/0949 ,  H05K2201/10545 ,  H05K2201/10689

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract translation: 多层印刷电路板包括：第一表面层，包括半导体集成电路;第二表面层，包括旁路电容器，并且与第一表面层相对;主电源布线层;以及第一表面层， 和第二表面层。 在多层印刷电路板中，旁路电容器的一个端子连接到从主电源布线层到半导体集成电路的电源端子的布线路径的中点，并且从第一布线路径的阻抗 到旁路电容器的端子的主电源布线层高于从旁路电容器的端子到半导体集成电路的电源端子的第二布线路径的阻抗。

公开(公告)号：US20080157343A1

公开(公告)日：2008-07-03

申请号：US11648220

申请日：2006-12-29

Applicant: Sriram Dattaguru ,  Larry Binder ,  Cengiz A. Palanduz ,  Chris Jones ,  Dave Bach ,  Kaladhar Radhakrishnan ,  Timothe Litt

Inventor： Sriram Dattaguru ,  Larry Binder ,  Cengiz A. Palanduz ,  Chris Jones ,  Dave Bach ,  Kaladhar Radhakrishnan ,  Timothe Litt

IPC: H01L23/13

CPC classification number: H05K1/0262 ,  H01L23/642 ,  H01L25/162 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/19106 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/0401

Abstract: In some embodiments, a ceramic interposer with silicon voltage regulator and array capacitor combination for integrated circuit packages is presented. In this regard, an apparatus is introduced having a bowl-shaped ceramic interposer containing conductive traces, one or more silicon voltage regulator(s) coupled with contacts on a first surface of the ceramic interposer, and one or more array capacitor(s) coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，提供了具有用于集成电路封装的硅电压调节器和阵列电容器组合的陶瓷插入器。 在这方面，引入了一种装置，其具有包含导电迹线的碗形陶瓷插入器，与陶瓷插入件的第一表面上的触点耦合的一个或多个硅电压调节器，以及一个或多个耦合的阵列电容器 在陶瓷插入件的第二表面上具有触点。 还公开并要求保护其他实施例。

公开(公告)号：US20080142256A1

公开(公告)日：2008-06-19

申请号：US12068992

申请日：2008-02-14

Applicant: Takashi Shuto ,  Kenji Takano ,  Kenji Iida ,  Kenichiro Abe ,  Keiji Arai ,  Kiyotaka Seyama

Inventor： Takashi Shuto ,  Kenji Takano ,  Kenji Iida ,  Kenichiro Abe ,  Keiji Arai ,  Kiyotaka Seyama

IPC: H05K3/02 ,  H05K1/11

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/183 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4644 ,  H05K3/4652 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2201/068 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/0156 ,  H05K2203/016 ,  H05K2203/061 ,  H05K2203/085 ,  H05K2203/1536 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49169 ,  H01L2224/0401

Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.

公开(公告)号：US20080106844A1

公开(公告)日：2008-05-08

申请号：US11972579

申请日：2008-01-10

Applicant: Cengiz Palanduz ,  Dustin Wood

Inventor： Cengiz Palanduz ,  Dustin Wood

IPC: H01G4/012 ,  H05K7/02

CPC classification number: H05K1/162 ,  H01G4/1209 ,  H01G4/20 ,  H01G4/33 ,  H01L2224/16225 ,  H05K1/0306 ,  H05K1/097 ,  H05K3/4629 ,  H05K3/4641 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10545 ,  Y10T29/435

Abstract: A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate comprising at least one capacitor structure formed on a surface, the capacitor structure comprising a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material comprises columnar grains.

Abstract translation: 一种方法，包括将包含一定量的陶瓷材料的纳米颗粒的胶体悬浮液沉积在基底上; 并对悬浮液进行热处理以形成薄膜。 一种方法，包括将陶瓷材料的多个纳米颗粒沉积在衬底的表面上的预定位置; 并对多个纳米颗粒进行热处理以形成薄膜。 一种包括计算设备的系统，包括微处理器，所述微处理器通过衬底耦合到印刷电路板，所述衬底包括形成在表面上的至少一个电容器结构，所述电容器结构包括第一电极，第二电极和陶瓷 设置在第一电极和第二电极之间的材料，其中陶瓷材料包括柱状晶粒。

公开(公告)号：US07360307B2

公开(公告)日：2008-04-22

申请号：US11283446

申请日：2005-11-18

Applicant: Zhiping Yang ,  Vinayagam Arumugham ,  Lekhanh Dang

Inventor： Zhiping Yang ,  Vinayagam Arumugham ,  Lekhanh Dang

IPC: H05K3/34 ,  H01K3/10

CPC classification number: H05K1/0231 ,  H05K1/114 ,  H05K2201/09418 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A circuit board module has an IC device, discrete components, and a circuit board structure in electrical communication with the IC device and the discrete component. The circuit board structure includes non-conductive material defining a top surface of the circuit board structure and a bottom surface of the circuit board structure, vias supported by the non-conductive material, top pads electrically coupled to the vias, and bottom pads electrically coupled to the vias. The top pads are disposed along the top surface of the circuit board structure and are soldered to IC device. The bottom pads are disposed along the bottom surface of the circuit board structure and are configured to solder to the discrete components. The bottom pads include a group of angled bottom pads which is soldered to a group of the discrete components substantially at 45 degree angles relative to sides of the IC device.

Abstract translation: 电路板模块具有与IC器件和分立部件电连通的IC器件，分立部件和电路板结构。 电路板结构包括限定电路板结构的顶表面和电路板结构的底表面的非导电材料，由非导电材料支撑的通孔，电耦合到通孔的顶部焊盘和电耦合的底部焊盘 到通道 顶焊盘沿着电路板结构的顶表面设置，并被焊接到IC器件。 底部焊盘沿着电路板结构的底表面设置并且被配置为焊接到分立部件。 底部焊盘包括一组倾斜的底部焊盘，其相对于IC器件的侧面基本上以45度角焊接到一组分立部件。

公开(公告)号：US07345558B2

公开(公告)日：2008-03-18

申请号：US11065448

申请日：2005-02-25

Applicant: Tetsuhide Okahashi

Inventor： Tetsuhide Okahashi

IPC: H03H7/00

CPC classification number: H03H7/38 ,  H05K1/18 ,  H05K2201/1003 ,  H05K2201/10545

Abstract: Coil(s) 11 and coil(s) 12 of LC resonant circuit(s) are oriented such that their centers are mutually perpendicular. For example, coil 11 might be mounted so as to stand upright on printed wiring board, and coil 12 might be mounted so as to lie flush against printed wiring board. Such configuration permitting lines of magnetic force from coil 11 and coil 12 to be oriented so as to be mutually perpendicular, lines of magnetic force from coil 11 and coil 12 do not merge, and coil 11 and coil 12 are not electromagnetically coupled. Accordingly, inductances of respective coils 11, 12 are unchanged; impedance frequency characteristics of respective LC resonant circuits are maintained at what they should be; and resonant impedance(s) is/are not lowered.

Abstract translation: LC谐振电路的线圈11和线圈12被定向成使得它们的中心相互垂直。 例如，可以将线圈11安装成在印刷线路板上竖立，并且线圈12可以安装成与印刷线路板齐平。 这样的配置允许来自线圈11和线圈12的磁力线被定向为相互垂直，来自线圈11和线圈12的磁力线不会合并，并且线圈11和线圈12不是电磁耦合的。 因此，各线圈11,12的电感不变; 各个LC谐振电路的阻抗频率特性保持在它们应该是什么; 并且谐振阻抗不降低。

公开(公告)号：US20080054430A1

公开(公告)日：2008-03-06

申请号：US11511815

申请日：2006-08-29

Applicant: Paul W. Coteus ,  Shawn A. Hall ,  Gareth G. Hougham ,  Alphonso P. Lanzetta ,  Rick A. Rand

Inventor： Paul W. Coteus ,  Shawn A. Hall ,  Gareth G. Hougham ,  Alphonso P. Lanzetta ,  Rick A. Rand

IPC: H01L23/02

CPC classification number: H05K3/325 ,  H05K2201/0314 ,  H05K2201/10545 ,  H05K2201/10719 ,  H05K2201/2018

Abstract: A package design is provided where a chip module is connected to a printed circuit board (PCB) via a land grid array (LGA) on the top surface of the PCB, and where a power supply is connected to the PCB via a second LGA on the bottom surface of the PCB. The stack of the chip module, power supply, and LGA is held in place and compressed with actuation hardware forming an adjustable frame. The package allows field replacibility of either the module, or the PS, and provides the shortest possible wiring distance from the PS to the module leading to higher performance.

Abstract translation: 提供了一种封装设计，其中芯片模块通过PCB顶表面上的焊盘网格阵列（LGA）连接到印刷电路板（PCB），并且电源通过第二个LGA连接到PCB PCB的底面。 芯片模块，电源和LGA的堆叠被保持就位并用致动硬件压缩形成可调节的框架。 该封装允许模块或PS的现场可替代性，并提供从PS到模块的最短可能布线距离，从而实现更高的性能。