公开(公告)号：US07888784B2

公开(公告)日：2011-02-15

申请号：US12242528

申请日：2008-09-30

Applicant: Charan Gurumurthy ,  Sanka Ganesan ,  Chandrashekhar Ramaswamy ,  Mark Hlad

Inventor： Charan Gurumurthy ,  Sanka Ganesan ,  Chandrashekhar Ramaswamy ,  Mark Hlad

IPC: H01L23/48

CPC classification number: H01L23/48 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/00 ,  H05K3/108 ,  H05K3/222 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10189 ,  H05K2201/10356 ,  H05K2201/1053 ,  H05K2201/10734 ,  H05K2203/167 ,  Y10T29/49124 ,  H01L2224/0401

Abstract: An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.

Abstract translation: 与柔性电缆互连的衬底封装的组件和衬底封装的制造方法。 该组件允许通过柔性电缆快速地在衬底封装之间传输输入/输出（I / O）信号，而不通过主板。 实施例涉及提供可分离的包装间柔性电缆连接的衬底封装。 在基板封装上提供密封导向孔，作为机械对准特征，以引导柔性电缆与基板封装上的高速I / O接触焊盘之间的连接。 制造方法的实施例涉及同时形成密封的引导通孔和I / O接触垫。

公开(公告)号：US07856710B2

公开(公告)日：2010-12-28

申请号：US11964355

申请日：2007-12-26

Applicant: Takashi Kariya ,  Akira Mochida

Inventor： Takashi Kariya ,  Akira Mochida

IPC: H01K3/10

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2203/0353 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of manufacturing a printed wiring board including preparing a high-dielectric capacitor sheet including a ceramic high-dielectric layer sandwiched by upper and lower electrode sheets, attaching the high-dielectric capacitor sheet to a first insulating layer, forming through holes for the upper and lower electrode sheets such that the through holes penetrate through the ceramic high-dielectric layer and upper and lower electrode sheets, forming a second insulating layer which fills the through holes and covers an upper surface of the high-dielectric capacitor sheet, forming an upper electrode connecting first hole, an upper electrode connecting second hole and a lower electrode connecting hole, filling the upper holes with conductive material such that the upper electrode connecting first hole and the upper electrode connecting second hole are connected to form an upper electrode connection portion, and filling the lower electrode connecting hole with conductive material to form a lower electrode connecting portion.

Abstract translation: 一种印刷电路板的制造方法，其特征在于，包括：制作包含由上下电极片夹着的陶瓷高电介质层的高介电电容器片，将所述高介电电容片贴附在第一绝缘层上， 和下电极片，使得通孔穿过陶瓷高介电层和上下电极片，形成填充通孔并覆盖高介电电容器片的上表面的第二绝缘层，形成上电极片 电极连接第一孔，上电极连接第二孔和下电极连接孔，用导电材料填充上孔，使得连接第一孔和连接第二孔的上电极的上电极连接形成上电极连接部， 并用导电材料填充下电极连接孔 m为下部电极连接部。

公开(公告)号：US07855894B2

公开(公告)日：2010-12-21

申请号：US11928397

申请日：2007-10-30

Applicant: Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K1/18

CPC classification number: H05K1/115 ,  H01G2/06 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/248 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract translation: 片状电容器20设置在印刷电路板10中。以这种方式，IC芯片90和每个片状电容器20之间的距离缩短，并且环路电感减小。 此外，芯片电容器20被容纳在具有大厚​​度的芯基板30中。 因此，印刷电路板的厚度不会变大。

公开(公告)号：US07827680B2

公开(公告)日：2010-11-09

申请号：US10751428

申请日：2004-01-06

Applicant: Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

Inventor： Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

IPC: H05K3/20

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An electroplating process of electroplating an electrically conductive substrate is described. The process includes electroplating intermittently to a predetermined plating thickness using the substrate surface as a cathode and a plating metal as an anode at a constant voltage between the anode and the cathode by repeating application of a voltage between a cathode and an anode and interruption of the application alternately. It is described that a voltage time/interruption time ratio is 0.1 to 1.0, a voltage time is not longer than 10 seconds, and an interruption time is not less than 1 x 10-12 seconds.

Abstract translation: 描述了对导电基板进行电镀的电镀工艺。 该工艺包括通过在阴极和阳极之间重复施加电压并使阴极和阳极之间的电压中断，在阳极和阴极之间以恒定电压将衬底表面作为阴极和电镀金属作为阳极间歇地电镀到预定的镀层厚度 交替应用。 描述了电压时间/中断时间比为0.1至1.0，电压时间不长于10秒，并且中断时间不小于1×10-12秒。

公开(公告)号：US07825500B2

公开(公告)日：2010-11-02

申请号：US12100653

申请日：2008-04-10

Applicant: Chien-Hao Wang

Inventor： Chien-Hao Wang

IPC: H01L23/48

CPC classification number: H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/186 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2203/063 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor device in the insulation layer. The substrate has a base, a first circuit layer, a second circuit layer, and at least a first conductive structure passing through the base and electrically connected to the first circuit layer and the second circuit layer. In addition, the third metal layer is patterned to form a third circuit layer having a plurality of third pads.

Abstract translation: 提供了一种用于嵌入式半导体器件的制造工艺。 在制造过程中，至少一个绝缘层和基板彼此堆叠，并且第三金属层层叠在绝缘层上以将半导体器件嵌入绝缘层中。 基板具有基极，第一电路层，第二电路层，以及至少第一导电结构，其通过基极并与第一电路层和第二电路层电连接。 此外，第三金属层被图案化以形成具有多个第三焊盘的第三电路层。

公开(公告)号：US07825340B2

公开(公告)日：2010-11-02

申请号：US12193492

申请日：2008-08-18

Applicant: Hitoshi Kashio

Inventor： Hitoshi Kashio

IPC: H05K1/11

CPC classification number: H05K1/0271 ,  H05K1/112 ,  H05K3/0017 ,  H05K3/064 ,  H05K2201/0394 ,  H05K2201/09063 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10734 ,  H05K2203/0554

Abstract: In one embodiment of the present invention, a connecting device of a double-sided wiring board includes a first-side connecting land portion configured by a first-side conductive layer and a first-side connecting conductive layer and a second-side connecting land portion configured by a second-side conductive layer; the first-side connecting land portion and the second-side connecting land portion face each other at respective central portions with an insulating substrate sandwiched therebetween; a substrate hole is formed corresponding to a peripheral end portion of the first-side connecting land portion and a peripheral end portion of the second-side connecting land portion; and the peripheral end portion of the first-side connecting land portion and the peripheral end portion of the second-side connecting land portion are connected to each other via the substrate hole.

Abstract translation: 在本发明的一个实施例中，双面布线板的连接装置包括由第一侧导电层和第一侧连接导电层构成的第一侧连接接地部分和第二侧连接接地部分 由第二侧导电层构成; 所述第一侧连接接地部和所述第二侧连接用接地部在各自的中央部彼此面对，并且将绝缘基板夹在其间; 与第一侧连接接地部的周缘部和第二侧连接接地部的周缘部对应地形成基板孔; 并且第一侧连接接地部分的周边端部和第二侧连接接地部分的周边端部经由基板孔相互连接。

公开(公告)号：US20100242271A1

公开(公告)日：2010-09-30

申请号：US12785037

申请日：2010-05-21

Applicant: Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

Inventor： Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

IPC: H05K3/00

CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09736 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4981 ,  Y10T407/1946 ,  Y10T407/1948 ,  H01L2924/00

Abstract: A dielectric structure including a metal foil, a dielectric layer and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 μm, the dielectric layer has a thickness of from 0.3 to 5 μm, and the conductor layer has a thickness of from 0.3 to 10 μm. The dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer. The vias of the dielectric layer have different diameters which are in a range of from 100 to 300 μm, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 μm, and a minimum via pitch is from 100 to 350 μm.

Abstract translation: 包括依次设置的金属箔，电介质层和导体层的电介质结构体，其中金属箔的厚度为10〜40μm，电介质层的厚度为0.3〜5μm，导体 层的厚度为0.3〜10μm。 电介质结构具有彼此分离并且穿透介电层和导体层两者的多个通孔。 电介质层的通孔具有不同的直径，范围为100〜300μm，导体层的通孔的直径大于电介质层的通孔的直径为5〜50μm ，最小通孔间距为100〜350μm。

公开(公告)号：US20100226108A1

公开(公告)日：2010-09-09

申请号：US12784634

申请日：2010-05-21

Applicant: Yasushi INAGAKI ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi INAGAKI ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/42

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed circuit board including a core substrate including a first resin substrate, a second resin substrate having an opening and a third resin substrate in a multilayer manner while interposing bonding plates, insulating layers and conductive circuit layers alternately laminated on the core substrate, solder bumps formed on an outer surface of the printed circuit board, a first capacitor formed in the opening of the second resin substrate, a conductive pad formed on the first resin substrate and connected to an electrode of the first capacitor, a via hole formed in the first resin substrate and directly connected to the conductive pad and a conductive circuit on the core substrate, and a second capacitor mounted on a surface of the printed circuit board.

Abstract translation: 一种印刷电路板，包括具有第一树脂基板的芯基板，具有开口的第二树脂基板和第三树脂基板，同时插入在芯基板上交替层叠的接合板，绝缘层和导电电路层，焊料凸块 形成在所述印刷电路板的外表面上的第一电容器，形成在所述第二树脂基板的开口中的第一电容器，形成在所述第一树脂基板上并连接到所述第一电容器的电极的导电焊盘， 树脂基板，并且直接连接到导电焊盘和芯基板上的导电电路，以及安装在印刷电路板的表面上的第二电容器。

公开(公告)号：US20100218891A1

公开(公告)日：2010-09-02

申请号：US12776771

申请日：2010-05-10

Applicant: Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

Inventor： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

IPC: C09J5/06

CPC classification number: H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4641 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1092

Abstract: A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

Abstract translation: 多层互连结构和形成方法。 在第一实施例中，第一和第二液晶聚合物（LCP）电介质层分别直接接合到导热层的第一和第二相对表面，没有外在粘合材料将导热层与第一或第二液晶聚合物 LCP电介质层。 在第二实施例中，第一和第二2S1P子结构分别直接接合到LCP电介质接合层的第一和第二相对表面，没有外部粘合材料将LCP电介质接合层与第一或第二2S1P子结构结合。

公开(公告)号：US20100212946A1

公开(公告)日：2010-08-26

申请号：US12489803

申请日：2009-06-23

Applicant: Keisuke SHIMIZU ,  Yoichiro KAWAMURA

Inventor： Keisuke SHIMIZU ,  Yoichiro KAWAMURA

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H05K1/185 ,  H01G4/33 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/188 ,  H05K3/06 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/0369 ,  H05K2203/0554 ,  H05K2203/063 ,  H05K2203/1469 ,  Y02P70/611 ,  Y10T29/49139 ,  H01L2924/00

Abstract: A wiring board including a substrate, an electronic component having an electrode and arranged inside the substrate, and a wiring layer formed over the substrate and connected to the electrode through a via hole. The electrode has a connection surface portion contacting the via hole, and the connection surface portion has a thickness which is made thinner than a thickness of the electrode surrounding the connection surface portion.

Abstract translation: 一种布线基板，包括基板，具有电极并布置在基板内部的电子部件，以及布线层，形成在基板上并通过通孔连接到电极。 电极具有接触通孔的连接表面部分，并且连接表面部分具有比围绕连接表面部分的电极的厚度更薄的厚度。