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    Deep reactive ion etching process and microelectromechanical devices formed thereby
    111.
    发明申请
    Deep reactive ion etching process and microelectromechanical devices formed thereby 失效

    公开(公告)号：US20020111031A1

    公开(公告)日：2002-08-15

    申请号：US09782394

    申请日：2001-02-14

    Inventor： Troy A. Chase ,  John C. Christenson

    IPC: H01L021/302 ,  H01L021/461

    CPC classification number: B81C1/00579 ,  B81C2201/0132 ,  G01P15/0802 ,  G01P15/0888 ,  G01P15/125

    Abstract: A process for forming a microelectromechanical system (MEMS) device by a deep reactive ion etching (DRIE) process during which a substrate overlying a cavity is etched to form trenches that breach the cavity to delineate suspended structures. In order to eliminate or at least reduce heat and/or charge accumulation that accelerates the DRIE etch rate of certain suspended structures, means are provided to electrically and/or thermally tie the suspended structures to each other and/or the surrounding bulk substrate. As a result, the process window is increased to allow slower-etching structures to be etched to completion without overetching the more rapidly-etched structures.

    Two etchant etch method
    112.
    发明授权
    Two etchant etch method 失效

    公开(公告)号：US06372655B2

    公开(公告)日：2002-04-16

    申请号：US09836934

    申请日：2001-04-17

    Applicant: Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

    Inventor： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

    IPC: H01L2100

    CPC classification number: H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

    Abstract: A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

    Manufacturing method of silicon device
    113.
    发明授权
    Manufacturing method of silicon device 失效
    硅器件的制造方法

    公开(公告)号：US06358861B1

    公开(公告)日：2002-03-19

    申请号：US09658864

    申请日：2000-09-08

    Applicant: Hiroshi Ohji ,  Kazuhiko Tsutsumi ,  Patrick J. French

    Inventor： Hiroshi Ohji ,  Kazuhiko Tsutsumi ,  Patrick J. French

    IPC: H01L21302

    CPC classification number: B81C1/00547 ,  B81C2201/0132 ,  H01L21/3063 ,  Y10S438/977

    Abstract: A method of manufacturing a silicon device with a single crystal structure, including forming etching start patterns on a surface of a silicon substrate; etching the silicon substrate by applying a voltage to the silicon substrate while the silicon substrate is immersed in a solution containing fluorine ions, with the silicon substrate used a positive electrode, to form narrow etched portions that extend into the substrate from the etching start patterns; and accelerating etching of the silicon substrate by increasing current flowing through the silicon substrate after the narrow etched portions have reached a predetermined depth, so that neighboring etched portions are in communication with each other below the narrow etched portions and a free standing structure including part of the silicon substrate is formed, and a hollow portion is formed below the free standing structure.

    Abstract translation: 一种制造具有单晶结构的硅器件的方法，包括在硅衬底的表面上形成蚀刻起始图案; 在将硅衬底浸入含有氟离子的溶液中时，通过向硅衬底施加电压来蚀刻硅衬底，硅衬底用正电极形成从蚀刻开始图案延伸到衬底中的窄蚀刻部分; 以及在窄蚀刻部分达到预定深度之后通过增加流过硅衬底的电流来加速硅衬底的蚀刻，使得相邻的蚀刻部分在窄蚀刻部分下方彼此连通，并且包括部分 形成硅衬底，并且在自立式结构之下形成中空部分。

    Micromechanical accelerometer for automotive applications
    116.
    发明授权
    Micromechanical accelerometer for automotive applications 有权
    用于汽车应用的微机械加速度计

    公开(公告)号：US06170332B2

    公开(公告)日：2001-01-09

    申请号：US09552578

    申请日：2000-04-19

    Applicant: Noel C. MacDonald ,  Kevin A. Shaw ,  Scott G. Adams

    Inventor： Noel C. MacDonald ,  Kevin A. Shaw ,  Scott G. Adams

    IPC: G01P1508

    CPC classification number: G01P15/131 ,  B81B2201/0235 ,  B81B2203/051 ,  B81C1/00619 ,  B81C2201/0132 ,  G01P1/006 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  G01P2015/0817

    Abstract: A micromechanical capacitive accelerometer is provided from a single silicon wafer. The basic structure of the micromechanical accelerometer is etched in the wafer to form a released portion in the substrate, and the released and remaining portions of the substrate are coated with metal under conditions sufficient to form a micromechanical capacitive accelerometer. The substrate is preferably etched using reactive-ion etching for at least the first etch step in the process that forms the basic structure, although in another preferred embodiment, all etching is reactive-ion etching. The accelerometer also may comprise a signal-conditioned accelerometer wherein signal-conditioning circuitry is provided on the same wafer from which the accelerometer is formed, and VLSI electronics may be integrated on the same wafer from which the accelerometer is formed. The micromechanical capacitive accelerometer can be used for airbag deployment, active suspension control, active steering control, anti-lock braking, and other control systems requiring accelerometers having high sensitivity, extreme accuracy and resistance to out of plane forces.

    Abstract translation: 从单个硅晶片提供微机电电容式加速度计。 在晶片中蚀刻微机械加速度计的基本结构，以在衬底中形成释放部分，并且在足以形成微机械电容式加速度计的条件下，用金属涂覆衬底的释放和剩余部分。 在形成基本结构的工艺中，优选使用反应离子蚀刻对至少第一蚀刻步骤蚀刻衬底，尽管在另一优选实施例中，所有蚀刻都是反应离子蚀刻。 加速度计还可以包括信号调节加速度计，其中信号调节电路设置在与其形成加速度计的同一晶片上，并且VLSI电子器件可以集成在形成加速度计的相同晶片上。 微机电容加速度计可用于安全气囊部署，主动悬架控制，主动转向控制，防抱死制动以及需要具有高灵敏度，极高精度和抗平面外力的加速度计的其他控制系统。

    Micromechanical system fabrication method using (111) single crystalline silicon
    117.
    发明授权
    Micromechanical system fabrication method using (111) single crystalline silicon 有权
    （111）单晶硅的微机械系统制造方法

    公开(公告)号：US6150275A

    公开(公告)日：2000-11-21

    申请号：US250519

    申请日：1999-02-16

    Applicant: Dong-Il Cho ,  Sangwoo Lee ,  Sangjun Park

    Inventor： Dong-Il Cho ,  Sangwoo Lee ,  Sangjun Park

    IPC: C23F1/00 ,  B81C1/00 ,  C30B33/00 ,  H01L21/311 ,  H01L21/302

    CPC classification number: C30B29/06 ,  B81C1/00801 ,  C30B33/00 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/014

    Abstract: Disclosed is a micromechanical system fabrication method using (111) single crystalline silicon as a silicon substrate and employing a reactive ion etching process in order to pattern a microstructure that will be separated from the silicon substrate and a selective release-etching process utilizing an aqueous alkaline solution in order to separate the microstructure from the silicon substrate. According to the micromechanical system fabrication method of the present invention, the side surfaces of microstructures can be formed to be vertical by employing the RIE technique. Furthermore, the microstructures can be readily separated from the silicon substrate by employing the selective release-etching technique using slow etching {111} planes as the etch stop in an aqueous alkaline solution. In addition, etched depths can be adjusted during the RIE step, thereby adjusting the thickness of the microstructure and the spacing between the microstructure and the silicon substrate.

    Abstract translation: 公开了一种使用（111）单晶硅作为硅衬底并采用反应离子蚀刻工艺以便将从硅衬底分离的微结构图案和利用碱性水溶液的选择性剥离蚀刻工艺的微机械系统制造方法 溶液以将微结构与硅衬底分离。 根据本发明的微机械系统制造方法，通过采用RIE技术，可以将微结构的侧面形成为垂直的。 此外，通过使用选择性剥离蚀刻技术，通过使用慢蚀刻{111}晶面作为碱性水溶液中的蚀刻停止，微结构可以容易地与硅衬底分离。 此外，可以在RIE步骤期间调整蚀刻深度，从而调整微结构的厚度和微结构与硅衬底之间的间隔。

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