公开(公告)号：US08028402B2

公开(公告)日：2011-10-04

申请号：US11775294

申请日：2007-07-10

Applicant: Hidehiro Nakamura ,  Akishi Nakaso ,  Shigeharu Arike ,  Fumio Inoue ,  Tetsuya Enomoto ,  Norio Moriike ,  Kousuke Hiroki

Inventor： Hidehiro Nakamura ,  Akishi Nakaso ,  Shigeharu Arike ,  Fumio Inoue ,  Tetsuya Enomoto ,  Norio Moriike ,  Kousuke Hiroki

IPC: H05K3/36 ,  H01R9/00 ,  H01K3/10

CPC classification number: H05K3/4617 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/244 ,  H05K3/4038 ,  H05K3/4623 ,  H05K3/4632 ,  H05K3/4647 ,  H05K2201/0141 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed is a manufacturing method of a multi-layer wiring board, which method includes: preparing connection boards, the connection boards having respectively an insulating resin composition layer, a connection conductor formed so as to pass through the insulating resin composition layer and a conductor circuit formed on the insulating resin composition layer and connected to the connection conductor; aligning the connection boards; and laminating the aligned connection boards by heating and pressing, so that the connection conductors, or the connection conductor and the conductor circuit, are conductively connected with each other, and the connection boards are mechanically connected with each other by the insulating resin composition layer. The connection boards are formed by specified processing, including use of a three-layer composite metallic layer.

Abstract translation: 公开了一种多层布线板的制造方法，该方法包括：准备连接板，连接板分别具有绝缘树脂组合物层，形成为穿过绝缘树脂组合物层的连接导体和导体电路 形成在绝缘树脂组合物层上并连接到连接导体; 对准连接板; 并且通过加热和压制层叠对准的连接板，使得连接导体或连接导体和导体电路彼此导电连接，并且连接板通过绝缘树脂组合物层彼此机械连接。 连接板通过特定的加工形成，包括使用三层复合金属层。

公开(公告)号：US20110236714A1

公开(公告)日：2011-09-29

申请号：US13123127

申请日：2009-10-13

Applicant: Shigeo Ohsaka ,  Toshio Kurosawa ,  Takashi Natsume

Inventor： Shigeo Ohsaka ,  Toshio Kurosawa ,  Takashi Natsume

IPC: B32B15/01 ,  C23C14/34 ,  C23C14/14

CPC classification number: C23C14/04 ,  C23C14/044 ,  C23C14/08 ,  C23C14/165 ,  C23C14/542 ,  C23C14/562 ,  H05K1/167 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2203/0361 ,  Y10T428/12493

Abstract: A copper foil with an electric resistance film in which a film with higher electrical resistivity than the metal foil is provided on the metal foil, wherein a plurality of electric resistance films with different electric resistance is arranged in parallel on the same metal foil. With conventionally used built-in resistor elements, one resistor element is configured of one type of substance on the copper foil. Nevertheless, when actually mounting the resistor elements, the circuit design tolerance can be increased and the number of man-hours can be reduced with two resistor elements and further with a plurality of resistor elements compared to a case with one resistor element. This invention aims to provide a metal foil with a built-in resistor element comprising two or more types of resistor elements on one metal foil.

Abstract translation: 在金属箔上设置有具有电阻率高于金属箔的膜的具有电阻膜的铜箔，其中在同一金属箔上平行布置具有不同电阻的多个电阻膜。 使用传统使用的内置电阻元件，一个电阻元件由铜箔上的一种物质构成。 然而，当实际安装电阻元件时，与一个电阻器元件相比，可以增加电路设计容差并且可以使用两个电阻元件减少工作时间，并且还可以减少多个电阻元件。 本发明的目的是提供一种具有内置电阻元件的金属箔，该金属箔在一个金属箔上包括两种或多种类型的电阻元件。

公开(公告)号：US20110226516A1

公开(公告)日：2011-09-22

申请号：US13024897

申请日：2011-02-10

Applicant: TSUTOMU TAKEDA

Inventor： TSUTOMU TAKEDA

IPC: H05K1/16

CPC classification number: H05K1/0251 ,  H01L2924/15311 ,  H01L2924/19051 ,  H05K1/0231 ,  H05K1/162 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/09809 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2203/0207 ,  H05K2203/1572

Abstract: A wiring board includes at least one signal layer, at least one ground layer, at least one power plane, at least one power supply via that electrically conducts wiring over one substrate surface where a semiconductor device chip is mounted, wiring over another substrate surface, and the power plane, and signal wiring for performing signal transmission between a plurality of semiconductor device chips. The power plane is placed to the one substrate surface side than the signal wiring. The power supply via is composed of a large diameter aperture and a small diameter aperture. The large diameter aperture has a relatively large diameter and is formed from the one substrate surface to the power plane, and the small diameter aperture has a relatively small diameter and is formed from the power plane to the other substrate surface.

Abstract translation: 布线板包括至少一个信号层，至少一个接地层，至少一个电力平面，至少一个电源通孔，该电源通过一个衬底表面上电导线，半导体器件芯片安装在一个衬底表面上，在另一个衬底表面上布线， 以及用于在多个半导体器件芯片之间进行信号传输的信号布线。 电源平面被放置在与信号布线相对的一个基板表面侧。 电源通孔由大直径孔径和小直径孔径组成。 大直径孔径具有相对大的直径，并且由一个基板表面到动力平面形成，并且小直径孔径具有相对较小的直径并且从动力平面形成到另一个基底表面。

公开(公告)号：US07985930B2

公开(公告)日：2011-07-26

申请号：US10921525

申请日：2004-08-19

Applicant: Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

IPC: H05K1/11

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A metal layer 18 is sandwiched between insulating layers 14 and 20 so that required strength is maintained. Hence it follows that the thickness of a core substrate 30 can be reduced and, therefore, the thickness of a multi-layer printed circuit board can be reduced. Formation of non-penetrating openings 22 which reach the metal layer 18 in the insulating layers 14 and 20 is simply required. Therefore, small non-penetrating openings 22 can easily be formed by applying laser beams. Thus, through holes 36 each having a small diameter can be formed.

Abstract translation: 金属层18夹在绝缘层14和20之间，从而保持所需的强度。 因此，可以减小芯基板30的厚度，因此可以减小多层印刷电路板的厚度。 仅仅需要在绝缘层14和20中到达金属层18的非穿透开口22的形成。 因此，通过施加激光束可以容易地形成小的非穿透开口22。 因此，可以形成各自具有小直径的通孔36。

公开(公告)号：US20110171491A1

公开(公告)日：2011-07-14

申请号：US13003159

申请日：2009-07-07

Applicant: Yuji Suzuki ,  Takahiro Saito

Inventor： Yuji Suzuki ,  Takahiro Saito

IPC: B32B3/00 ,  B22D7/00

CPC classification number: C25D1/04 ,  C25D5/50 ,  C25D7/0614 ,  H05K1/0393 ,  H05K1/09 ,  H05K2201/0355 ,  H05K2203/1105 ,  Y10T428/12 ,  Y10T428/12993

Abstract: To provide an electrodeposited copper foil having flexibility and bending property equivalent to or better than that of rolled copper foil, an electrodeposited copper foil wherein regarding a crystal structure after heat treatment is applied to the electrodeposited copper foil wherein LMP defined as formula 1 is 9000 or more, either color tone of a red system or a blue system occupies 80% or more in a surface in the EBSP analysis is provided. LMP=(T+273)*(20+Log t)  Formula 1 wherein 20 is a material constant of copper, T is temperature (° C.), and t is time (Hr). Preferably, relative intensity of (331) face against (111) face is 15 or more in the X-ray diffraction of the electrodeposited copper foil after the heat treatment is applied to the electrodeposited copper foil.

Abstract translation: 为了提供具有与轧制铜箔相当或更好的柔软性和弯曲性能的电解铜箔，将其中将热处理后的晶体结构施加到电解铜箔上的电沉积铜箔，其中定义为式1的LMP为9000或 提供了在EBSP分析中，红色系统或蓝色系统的色调在表面中占据80％以上。 LMP =（T + 273）*（20 + Log t）式1其中20是铜的材料常数，T是温度（℃），t是时间（Hr）。 优选地，在对电沉积铜箔进行热处理之后，电解铜箔的X射线衍射中，（331）面对（111）面的相对强度为15以上。

公开(公告)号：US07977577B2

公开(公告)日：2011-07-12

申请号：US11910142

申请日：2007-02-14

Applicant: Hyung Wook Lee

Inventor： Hyung Wook Lee

IPC: H05K1/00

CPC classification number: H05K3/361 ,  H01L2224/48091 ,  H05K1/0393 ,  H05K3/064 ,  H05K3/281 ,  H05K3/323 ,  H05K3/4611 ,  H05K3/4635 ,  H05K3/4691 ,  H05K3/4694 ,  H05K2201/0191 ,  H05K2201/0355 ,  H05K2201/043 ,  H05K2201/09127 ,  H05K2201/09972 ,  H01L2924/00014

Abstract: Disclosed are a multi-layer flexible printed circuit board and a method for manufacturing the same. The multi-layer flexible printed circuit board includes an adhesion sheet from which a pressing and heating area is cut, an upper base layer, from which the pressing and heating area is cut, on the adhesion sheet, and a lower base layer under to the adhesion sheet.

Abstract translation: 公开了一种多层柔性印刷电路板及其制造方法。 多层柔性印刷电路板包括：加压区域被切割的粘合片，粘合片上的加压区域被切割的上基层和下基层 粘合片。

公开(公告)号：US07973248B2

公开(公告)日：2011-07-05

申请号：US12219381

申请日：2008-07-21

Applicant: Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Youn-Soo Seo ,  Hee-Bum Shin ,  Yoong Oh ,  Byung-Bae Seo ,  Tae-Kyoung Kim ,  Dong-Jin Park

Inventor： Jee-Soo Mok ,  Chang-Sup Ryu ,  Eung-Suek Lee ,  Youn-Soo Seo ,  Hee-Bum Shin ,  Yoong Oh ,  Byung-Bae Seo ,  Tae-Kyoung Kim ,  Dong-Jin Park

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/462 ,  H01R12/523 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0353 ,  Y10T29/49155

Abstract: A printed circuit board using paste bumps and manufacturing method thereof are disclosed. The method of manufacturing a printed circuit board using paste bumps, includes: (a) perforating a core board to form at least one via hole, (b) filling the at least one via hole by fill-plating and forming a circuit pattern on at least one surface of the core board, (c) stacking a paste bump board on at least one surface of the core board, and (d) forming an outer layer circuit on a surface of the paste bump board, a structurally stable all-layer IVH structure can be implemented due to increased strength in the BVH's of the plated core boards, the manufacture time can be reduced due to parallel processes and collective stacking, implementing micro circuits can be made easy due to the copper foils of the paste bump boards stacked on the outermost layers, the manufacture costs can be reduced as certain plating and drilling processes may be omitted, the interlayer connection area is increased between circuit patterns for improved connection reliability, and dimple coverage can be obtained.

Abstract translation: 公开了一种使用糊状凸块的印刷电路板及其制造方法。 使用糊状凸块制造印刷电路板的方法包括：（a）穿孔芯板以形成至少一个通孔，（b）通过填充电镀填充至少一个通孔并在其上形成电路图案 芯板的至少一个表面，（c）在芯板的至少一个表面上堆叠焊料凸块，以及（d）在焊料凸块的表面上形成外层电路，结构稳定的全层 由于镀层芯板的BVH的强度增加，可以实现IVH结构，由于并行处理和集体堆叠，制造时间可以减少，由于粘贴凸块的铜箔堆叠而实现微电路变得容易 在最外层，可以减少制造成本，因为可以省略某些电镀和钻孔工艺，在电路图案之间增加层间连接面积以提高连接可靠性，并且可以获得凹坑覆盖 d。

公开(公告)号：US07968803B2

公开(公告)日：2011-06-28

申请号：US11658877

申请日：2006-07-07

Applicant: Hideki Higashitani

Inventor： Hideki Higashitani

IPC: H05K1/11

CPC classification number: H05K3/4069 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/384 ,  H05K3/4614 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0373 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/1461 ,  Y10T29/49124

Abstract: A wiring substrate of the invention comprises an electrical insulation substrate (1), a through-hole (3) formed in the electrical insulation substrate, electrically conductive paste (4) filled inside the through-hole, and wiring traces (11) formed on one or both surfaces of the electrical insulation substrate and electrically connected with the electrically conductive paste, wherein interfaces of the wiring traces in contact with the electrically conductive paste have at least one of an asperate surface and a smooth surface, and a plurality of granular bumps (14) formed further thereon.

Abstract translation: 本发明的布线基板包括电绝缘基板（1），形成在电绝缘基板中的通孔（3），填充在通孔内部的导电浆料（4）和形成在通孔 电绝缘基板的一个或两个表面并与导电浆料电连接，其中与导电浆料接触的布线迹线的界面具有平坦表面和光滑表面中的至少一个，以及多个颗粒凸块 （14）。

公开(公告)号：US20110139626A1

公开(公告)日：2011-06-16

申请号：US12997420

申请日：2009-06-12

Applicant: Takahiro Saito ,  Yuji Suzuki ,  Shoya Iuchi ,  Tetsuji Nishikawa

Inventor： Takahiro Saito ,  Yuji Suzuki ,  Shoya Iuchi ,  Tetsuji Nishikawa

IPC: C25D3/38 ,  C25D7/00

CPC classification number: C25D7/0614 ,  C25D1/04 ,  C25D3/38 ,  C25D5/50 ,  C25D7/0635 ,  H05K1/0393 ,  H05K1/09 ,  H05K2201/0355 ,  H05K2203/1105

Abstract: An object of the present invention is to provide an electrolytic copper coating that exhibits a bendability and flexibility equal to or better than those of rolled copper foil after the heat history in a circuit board fabrication process, especially after a heat history equivalent to the heat history applied when bonding with a polyimide film. The present invention provides an electrolytic copper coating and a method of manufacturing the same wherein, when performing heat treatment so that the LMP value shown in Equation 1 becomes 9000 or more, the result becomes a crystal distribution of crystal grains, having a maximum length of crystal grains after heat treatment of 10 μm or more, of 70% or more: LMP=(T+273)*(20+Log t)  Equation 1 where, 20 is a material constant of copper, T is temperature (° C.), and t is time (hr).

Abstract translation: 本发明的目的是提供一种电解铜涂层，其在电路板制造工艺中的热历史之后具有等于或优于轧制铜箔的弯曲性和柔性，特别是在与热历史相当的热历史之后 当与聚酰亚胺膜接合时施加。 本发明提供一种电解铜涂层及其制造方法，其中，当进行热处理使得等式1所示的LMP值变为9000以上时，结果成为具有最大长度的晶粒的晶体分布 热处理后的晶粒为10μm以上，70％以上：LMP =（T + 273）*（20 + Log t）式1其中，20为铜的材料常数，T为温​​度（℃） ），t为时间（小时）。

公开(公告)号：US07935891B2

公开(公告)日：2011-05-03

申请号：US12068992

申请日：2008-02-14

Applicant: Takashi Shuto ,  Kenji Takano ,  Kenji Iida ,  Kenichiro Abe ,  Keiji Arai ,  Kiyotaka Seyama

Inventor： Takashi Shuto ,  Kenji Takano ,  Kenji Iida ,  Kenichiro Abe ,  Keiji Arai ,  Kiyotaka Seyama

IPC: H05K1/03

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/183 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4644 ,  H05K3/4652 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2201/068 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/0156 ,  H05K2203/016 ,  H05K2203/061 ,  H05K2203/085 ,  H05K2203/1536 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49169 ,  H01L2224/0401

Abstract: The present invention relates to a method of manufacturing a wiring board comprising: a build-up layer, in which wiring patterns are piled with insulating layers; and a core substrate, which is separately formed from the build-up layer, the method comprising the steps of: separably forming the build-up layer on a plate-shaped support; electrically connecting the core substrate to the wiring patterns of the build-up layer on the support; and removing the support from the build-up layer so as to form the wiring board, in which the build-up layer is connected to the core substrate. By separably forming the build-up layer and the core substrate, the wiring board effectively exhibiting characteristics thereof can be produced.

Abstract translation: 本发明涉及一种制造布线板的方法，包括：堆叠层，其中布线图案用绝缘层堆叠; 以及与所述堆积层分开形成的芯基板，所述方法包括以下步骤：在板状支撑体上可分离地形成所述堆积层; 将芯基板电连接到支撑体上的堆积层的布线图案; 并且从堆积层移除支撑体，以形成其中堆积层连接到芯基板的布线板。 通过可分离地形成积层和芯基板，可以制造有效显示其特性的布线板。