公开(公告)号：US20160322127A1

公开(公告)日：2016-11-03

申请号：US15038138

申请日：2014-12-03

Applicant: JUNKOSHA INC.

Inventor： Tomohiro Adachi ,  Shunsuke Munakata

IPC: H01B7/04 ,  H01B7/42 ,  H02G3/04 ,  H01B9/00

CPC classification number: H01B7/04 ,  A61B1/0011 ,  B29K2027/18 ,  G02B6/4416 ,  G02B6/443 ,  H01B7/048 ,  H01B7/425 ,  H01B9/005 ,  H01B11/02 ,  H02G3/0437 ,  H05K2201/0116

Abstract: [Problem] To provide a composite cable, which, as an entire composite cable, ensures a stable quality while being flexible and manipulable [Solution] A composite cable having, on the inside of a sheath, a tube and a plurality of cables. When said composite cable is suspended in a hoop shape with the entire composite cable as a cable to be tested, if the maximum value for the inner diameter of said hoop is measured as D1 and the inner diameter of the hoop at a position 100 mm from the top edge of the hoop when the hoop is subjected to a load of 1 kg is measured as D2, the condition D1-D2>70 mm is satisfied. The tube partially or entirely comprises a layer made from porous polytetrafluoroethylene, and if the outer diameter and the inner diameter of the layer of the tube are respectively defined as (D) and (d), the condition (D-d)/D falls within the range of 0.27 to 0.75, and has a predetermined porous structure inside a region obtained by joining the following four points: the two points at which the average crevasse width of the porous structure in said ePTFE has a minimum value of 10.0 μm and a maximum value of 20.0 μm when the ratio (D-d)/D is 0.27, and the two points at which the minimum value is 16.0 μm and the maximum value is 27.0 μm when the ratio (D-d)/D is 0.75.

Abstract translation: [问题]提供一种复合电缆，其作为整个复合电缆确保了柔性和可操纵性的稳定质量[解决方案]一种复合电缆，其在护套的内侧具有管和多个电缆。 当所述复合电缆以整个复合电缆作为要测试的电缆悬挂在环形中时，如果所述箍的内径的最大值被测量为D1，并且将箍的内径测量在距离 将环箍承受1kg的载荷时的箍的上边缘测定为D2，满足条件D1-D2> 70mm。 管部分或全部由多孔聚四氟乙烯制成，如果管的外径和内径分别定义为（D）和（d），条件（Dd）/ D落在 范围为0.27〜0.75，并且在通过连接以下四点获得的区域内具有预定的多孔结构：所述ePTFE中的多孔结构的平均裂缝宽度具有最小值为10.0μm的两个点和最大值 当比率（Dd）/ D为0.27时，最小值为16.0μm的两个点和最大值为27.0μm时，当比率（Dd）/ D为0.75时，为20.0μm。

公开(公告)号：US20160286644A1

公开(公告)日：2016-09-29

申请号：US15154198

申请日：2016-05-13

Applicant: Cambridge Nanotherm Limited ,  Rogers Corporation

Inventor： Pavel SHASHKOV ,  Sergey USOV ,  Steven CURTIS ,  Brett W. KILHENNY

IPC: H05K1/11 ,  H05K3/40 ,  H05K1/09 ,  H05K1/03 ,  H05K1/05 ,  H05K1/02

CPC classification number: H05K1/0206 ,  C22C21/00 ,  H01L21/486 ,  H01L21/4871 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/49822 ,  H01L23/49827 ,  H01L33/62 ,  H01L33/641 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2924/13055 ,  H05K1/0271 ,  H05K1/053 ,  H05K3/445 ,  H05K3/4623 ,  H05K2201/0116 ,  H05K2201/068 ,  H05K2201/10106 ,  H05K2203/0723 ,  Y10T29/49169 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A metal substrate with insulated vias (MSIV) has a metallic layer with through-holes defined through a thickness of the layer, a dielectric layer formed on part of the surface of the metallic layer and extending to cover internal walls of the through-hole, a conductive material extending through the insulated through-hole to form an insulated via, and an electrical circuit formed on a portion of the dielectric layer in thermal and/or electrical contact with the conductive via. The dielectric layer is a dielectric nanoceramic layer having an equiaxed crystalline structure with an average grain size of 500 nanometres or less, a thickness of between 0.1 and 100 micrometres, a dielectric strength of greater than 20 KV mm−1, and a thermal conductivity of greater than 3 W/mK. Such a MSIV can be used as an electronic substrate to support devices such as power, microwave, optoelectronic, solid-state lighting and thermoelectric devices.

Abstract translation: 具有绝缘通孔（MSIV）的金属基板具有通过所述层的厚度限定的通孔的金属层，形成在金属层表面的一部分上并延伸以覆盖通孔的内壁的电介质层， 延伸穿过绝缘通孔形成绝缘通孔的导电材料，以及形成在与导电通孔热接触和/或电接触的介电层的一部分上的电路。 电介质层是具有平均晶粒尺寸为500纳米或更小，厚度为0.1至100微米，介电强度大于20KV /毫米-1的等轴晶体结构的电介质纳米陶瓷层，以及导热系数 大于3 W / mK。 这样的MSIV可以用作电子基板来支持诸如电力，微波，光电子，固态照明和热电装置的装置。

公开(公告)号：US09435527B1

公开(公告)日：2016-09-06

申请号：US14504705

申请日：2014-10-02

Applicant: UNIVERSAL LIGHTING TECHNOLOGIES, INC.

Inventor： Theodore E. Kluska ,  Travis L. Berry

IPC: F21V29/00 ,  F21V5/04 ,  F21V19/00 ,  F21Y101/02

CPC classification number: F21V3/00 ,  F21V29/83 ,  F21Y2105/10 ,  F21Y2115/10 ,  H05K1/0272 ,  H05K3/0061 ,  H05K2201/0116 ,  H05K2201/09063 ,  H05K2201/10106 ,  H05K2203/1178

Abstract: A light emitting apparatus includes a substrate, a light emitter mounted on the substrate, and a lens at least partially covering the light emitter, the lens defining a space about the light emitter. A heat sink is attached to the substrate. The heat sink is configured to dissipate heat from the light emitter via the substrate. The substrate includes an opening communicated with the space. A vent passage is at least partially defined between the heat sink and the substrate, the vent passage communicating the opening in the substrate with an exterior of the heat sink.

Abstract translation: 发光装置包括基板，安装在基板上的光发射器和至少部分地覆盖光发射器的透镜，透镜限定围绕光发射器的空间。 散热器附着在基板上。 散热器被配置为经由衬底从光发射器散发热量。 基板包括与该空间连通的开口。 排气通道至少部分地限定在散热器和基板之间，排气通道将基板中的开口与散热器的外部连通。

公开(公告)号：US09408294B2

公开(公告)日：2016-08-02

申请号：US14210759

申请日：2014-03-14

Applicant: General Electric Company

Inventor： Davide Jonathan Leone

IPC: H02H5/00 ,  H05K1/02 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K1/0201 ,  H05K1/0262 ,  H05K3/0064 ,  H05K3/3447 ,  H05K2201/0116 ,  H05K2201/10151 ,  H05K2203/0278 ,  H05K2203/1136

Abstract: Printed circuit board assemblies providing fault detection are provided. One example printed circuit board assembly includes a substrate layer. One or more solder pins are located on a rear surface of the substrate layer. The printed circuit board assembly includes a non-conductive layer adjacent to the rear surface of the substrate layer. The printed circuit board assembly includes a conductive layer adjacent to the non-conductive layer. The conductive layer is electrically connected to a ground. The printed circuit board assembly includes a mounting surface. The printed circuit board assembly includes a support layer compressed between the conductive layer and the mounting surface. The support layer applies a mechanical force that presses the conductive layer towards the non-conductive layer.

Abstract translation: 提供了提供故障检测的印刷电路板组件。 一个示例性印刷电路板组件包括基底层。 一个或多个焊针位于衬底层的后表面上。 印刷电路板组件包括与衬底层的后表面相邻的非导电层。 印刷电路板组件包括与非导电层相邻的导电层。 导电层电连接到地面。 印刷电路板组件包括安装表面。 印刷电路板组件包括在导电层和安装表面之间压缩的支撑层。 支撑层施加将导电层压向非导电层的机械力。

公开(公告)号：US20160186352A1

公开(公告)日：2016-06-30

申请号：US13984096

申请日：2012-02-07

Applicant: Pavel SHASHKOV ,  Gennady KHOMUTOV ,  Aleksey YEROKHIN ,  Sergey USOV

Inventor： Pavel SHASHKOV ,  Gennady KHOMUTOV ,  Aleksey YEROKHIN ,  Sergey USOV

IPC: C25D5/18 ,  C25D21/12 ,  C25D11/30 ,  C25D11/26 ,  C25D15/00 ,  C25D11/04

CPC classification number: C25D5/18 ,  C25D11/00 ,  C25D11/005 ,  C25D11/02 ,  C25D11/024 ,  C25D11/026 ,  C25D11/04 ,  C25D11/06 ,  C25D11/26 ,  C25D11/30 ,  C25D11/32 ,  C25D13/02 ,  C25D15/00 ,  C25D21/12 ,  H01L23/142 ,  H01L23/3677 ,  H01L23/3735 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13055 ,  H05K1/021 ,  H05K1/053 ,  H05K1/115 ,  H05K1/18 ,  H05K2201/0116 ,  H05K2203/0315 ,  H05K2203/1147 ,  Y10T428/1317 ,  Y10T428/24917 ,  Y10T428/249969 ,  H01L2924/00

Abstract: A method of forming a non-metallic coating on a metallic substrate involves the steps of positioning the metallic substrate in an electrolysis chamber and applying a sequence of voltage pulses of alternating polarity to electrically bias the substrate with respect to an electrode. Positive voltage pulses anodically bias the substrate with respect to the electrode and negative voltage pulses cathodically bias the substrate with respect to the electrode. The amplitude of the positive voltage pulses is potentiostatically controlled, wheras the amplitude of the negative voltage pulses is galvanostatically controlled.

Abstract translation: 在金属基材上形成非金属涂层的方法包括以下步骤：将金属基材定位在电解室中，并且施加一系列交替极性的电压脉冲以相对于电极使基板电偏置。 正电压脉冲相对于电极阳极偏置衬底，负电压脉冲相对于电极阴极偏置衬底。 正电压脉冲的幅度被电位控制，从而恒定地控制负电压脉冲的幅度。

公开(公告)号：US09295131B2

公开(公告)日：2016-03-22

申请号：US14383591

申请日：2013-03-01

Applicant: OLEDWORKS GMBH

Inventor： Dirk Hente

IPC: G09G3/10 ,  H05B33/08 ,  H01L27/32 ,  H05K1/02 ,  F21V29/00 ,  H05K1/18

CPC classification number: H05B33/0896 ,  F21V29/502 ,  F21V29/89 ,  H01L27/3204 ,  H01L2251/5361 ,  H05B33/0821 ,  H05K1/0201 ,  H05K1/0209 ,  H05K1/182 ,  H05K2201/0116 ,  H05K2201/062 ,  H05K2201/10022 ,  H05K2201/10106

Abstract: The invention relates to an electroluminescent lighting device, which is based on an array of standard electroluminescent tiles (D1-Dn) combined with an array of ballast components (R1-Rn) mounted on a carrier board (30) in such a way that the power loss is evenly spread across the whole board area to minimize local electric power in the ballast components. The unavoidable remaining hot spots and electroluminescent tiles are thermally coupled in such a way that the additional thermal load on the electroluminescent emission layer is as symmetric as possible with respect to the self heating of the electroluminescent device. This can be achieved by a combination of properly designed heat spreading and thermal isolation of the electroluminescent and ballast components. Heat spreading is achieved by a properly designed interconnection structure (40) on the carrier board. Different options are proposed to thermally isolate the electroluminescent tiles from the hot spots.

Abstract translation: 本发明涉及一种电致发光照明装置，其基于与安装在载体板（30）上的镇流器组件阵列（R1-Rn）组合的标准电致发光瓦片（D1-Dn）的阵列， 功率损耗均匀分布在整个电路板区域上，以最大限度地减少镇流器部件的局部电力。 不可避免的剩余热点和电致发光瓦片以这样的方式热耦合，使得电致发光发射层上的附加热负荷相对于电致发光器件的自身加热尽可能对称。 这可以通过适当设计的电致发光和镇流器部件的散热和热隔离的组合来实现。 通过在载板上的适当设计的互连结构（40）实现散热。 提出了不同的选择以将电致发光瓦片与热点隔离。

公开(公告)号：US20160073497A1

公开(公告)日：2016-03-10

申请号：US14943747

申请日：2015-11-17

Applicant: BYD COMPANY LIMITED

Inventor： Qiang XU ,  Xinping LIN

IPC: H05K1/05 ,  H05K3/18 ,  H05K3/44

CPC classification number: H05K1/053 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/1868 ,  C23C18/1879 ,  C23C18/40 ,  C25D11/08 ,  C25D11/10 ,  C25D11/16 ,  C25D11/246 ,  H05K3/185 ,  H05K3/44 ,  H05K2201/0116 ,  H05K2203/0315 ,  H05K2203/107 ,  H05K2203/1147

Abstract: Embodiments of the present disclosure are directed to a circuit board. The circuit board comprises: an aluminum-based substrate; an alumina layer formed on at least one surface of the aluminum-based substrate; and a circuit layer formed on the alumina layer. The alumina layer comprises alumina and an element selected from a group consisting of chromium, nickel, a rare earth metal, and a combination thereof.

Abstract translation: 本公开的实施例涉及电路板。 电路板包括：铝基底板; 形成在所述铝基基板的至少一个表面上的氧化铝层; 以及形成在氧化铝层上的电路层。 氧化铝层包括氧化铝和选自铬，镍，稀土金属及其组合的元素。

公开(公告)号：US09254993B2

公开(公告)日：2016-02-09

申请号：US12742179

申请日：2008-11-14

Applicant: Hermann Oppermann

Inventor： Hermann Oppermann

IPC: B81B7/00 ,  H05K3/00 ,  C22C1/02 ,  C22C1/08 ,  H01L23/00 ,  H05K3/24 ,  H05K3/38 ,  H05K3/28

CPC classification number: B81B7/0006 ,  C22C1/02 ,  C22C1/08 ,  H01L24/28 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/09701 ,  H05K3/24 ,  H05K3/28 ,  H05K3/383 ,  H05K2201/0116 ,  H05K2203/0361

Abstract: The invention relates to a method for connecting a precious metal surface to a polymer, wherein a layer made of 20% to 40% gold and 60% to 80% silver is deposited on a substrate and the silver is subsequently selectively removed in order to produce a nanoporous gold layer. A fluid polymer is applied to the gold layer and cured.

Abstract translation: 本发明涉及一种将贵金属表面连接到聚合物上的方法，其中将由20％至40％的金和60％至80％的银制成的层沉积在基底上，随后选择性地除去银，以便产生 纳米多孔金层。 将流体聚合物施加到金层并固化。

公开(公告)号：US20150349565A1

公开(公告)日：2015-12-03

申请号：US14822478

申请日：2015-08-10

Applicant: International Business Machines Corporation

Inventor： Mark C. Lamorey ,  Janak G. Patel ,  Peter Slota, JR. ,  David B. Stone

IPC: H02J7/00 ,  H01L25/16 ,  H01L23/552 ,  H01L23/367

CPC classification number: H01L23/552 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1624 ,  H01L2224/17181 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/16747 ,  H02J7/0042 ,  H02J7/0052 ,  H02J7/345 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/144 ,  H05K1/162 ,  H05K2201/0116 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/0999 ,  H05K2201/10515 ,  H05K2201/1056 ,  H01L2924/014 ,  H01L2924/00

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

公开(公告)号：US20150243937A1

公开(公告)日：2015-08-27

申请号：US14712024

申请日：2015-05-14

Applicant: Apple Inc.

Inventor： Richard Hung Minh Dinh ,  Richard P. Howarth ,  Peggy J. Jensen ,  John Chan ,  Patrick Kwok-Yeung Ng

IPC: H01M2/02 ,  B41F17/00

CPC classification number: H05K9/0024 ,  B32B17/061 ,  B41F17/00 ,  G03B15/03 ,  G06F1/1626 ,  G06F1/1656 ,  H01L23/24 ,  H01L23/296 ,  H01L23/3737 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6644 ,  H01M2/026 ,  H01M2/0292 ,  H01M2220/30 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451 ,  H04M1/0277 ,  H05K1/0203 ,  H05K1/0215 ,  H05K1/181 ,  H05K1/189 ,  H05K3/341 ,  H05K3/3447 ,  H05K3/363 ,  H05K2201/0116 ,  H05K2201/0162 ,  H05K2201/056 ,  H05K2201/10106 ,  H05K2201/10121 ,  H05K2201/10371 ,  H05K2201/10409 ,  H05K2201/2009 ,  H05K2203/1316 ,  Y02P70/613 ,  Y10T29/4911

Abstract: Electronic devices may be provided that include mechanical and electronic components. Connectors may be used to interconnect printed circuits and devices mounted to printed circuits. Printed circuits may include rigid printed circuit boards and flexible printed circuit boards. Heat sinks and other thermally conductive structures may be used to remove excess component heat. Structures may also be provided in an electronic device to detect moisture. Integrated circuits and other circuitry may be mounted on a printed circuit board under a radio-frequency shielding can.

Abstract translation: 可以提供包括机械和电子部件的电子设备。 连接器可用于连接安装到印刷电路的印刷电路和器件。 印刷电路可以包括刚性印刷电路板和柔性印刷电路板。 散热片和其他导热结构可用于去除多余的部件热量。 也可以在电子设备中提供结构以检测湿气。 集成电路和其他电路可以安装在射频屏蔽罐下的印刷电路板上。