公开(公告)号：US20150129292A1

公开(公告)日：2015-05-14

申请号：US14365070

申请日：2012-12-11

Applicant: THALES

Inventor： Bernard Ledain ,  Dominique Henriot ,  Philippe Kertesz

IPC: H05K3/46 ,  H05K1/09 ,  H05K1/11 ,  H05K1/03

CPC classification number: H05K3/4623 ,  H05K1/0313 ,  H05K1/09 ,  H05K1/115 ,  H05K3/4614 ,  H05K2201/0129 ,  H05K2201/041 ,  H05K2201/10378 ,  H05K2203/063 ,  Y10T29/49124

Abstract: A process is provided for producing a printed circuit board comprising at least two elementary circuit boards drilled with metallized holes the mouth of which is covered with a first metal, and at least one first intermediate layer, made of a compressible material, drilled with holes facing the elementary circuit boards and the mouth of which is covered with a second metal, which layer is placed between the two elementary circuit boards and soldered to each of the circuits by thermodiffusion of two metals forming an alloy at a formation temperature of the alloy. At least two second intermediate layers, the second layers not covering the first and second metal, being thermoplastics and having a melting point above the formation temperature of the alloy, are placed between the first intermediate layer and the elementary circuit boards.

Abstract translation: 提供了一种用于生产印刷电路板的方法，该印刷电路板包括至少两个基本电路板，所述至少两个基本电路板钻有金属化孔，其孔被第一金属覆盖，以及至少一个由可压缩材料制成的第一中间层， 基本电路板，其口部被第二金属覆盖，该层被放置在两个基本电路板之间，并且通过在合金的形成温度下形成合金的两种金属的热扩散而被焊接到每个电路。 至少两个第二中间层，不覆盖第一和第二金属的第二层是热塑性塑料并且具有高于合金的形成温度的熔点，放置在第一中间层和基本电路板之间。

公开(公告)号：US20150115467A1

公开(公告)日：2015-04-30

申请号：US14457094

申请日：2014-08-11

Applicant: Kyol PARK ,  JICHUL KIM ,  YUNHYEOK IM ,  Eon Soo JANG

Inventor： Kyol PARK ,  JICHUL KIM ,  YUNHYEOK IM ,  Eon Soo JANG

IPC: H01L23/522 ,  H05K1/02 ,  H05K1/11 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/552 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/0207 ,  H05K1/141 ,  H05K2201/10378 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be disposed between a lower semiconductor package and an upper semiconductor package to rapidly exhaust heat generated from a lower semiconductor chip included in the lower semiconductor package. The interposer substrate may be formed of one or more insulating layers, conductive vias, heat dissipating members, protection layers, and various conductive patterns.

Abstract translation: 本发明的概念提供了封装封装（PoP）器件。 在PoP器件中，可以在下半导体封装和上半导体封装之间设置插入器衬底和热边界材料层，以快速排出由下半导体封装中包括的下半导体芯片产生的热。 插入器基板可以由一个或多个绝缘层，导电通孔，散热构件，保护层和各种导电图案形成。

公开(公告)号：US20150092378A1

公开(公告)日：2015-04-02

申请号：US14040637

申请日：2013-09-28

Applicant: Mihir K. ROY ,  Mathew J. MANUSHAROW

Inventor： Mihir K. ROY ,  Mathew J. MANUSHAROW

IPC: H05K1/11 ,  H05K3/18 ,  H05K3/10 ,  H05K3/20 ,  H05K3/00

CPC classification number: H05K1/116 ,  H05K1/141 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/107 ,  H05K3/182 ,  H05K3/207 ,  H05K3/422 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49128

Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.

Abstract translation: 安装集成电路芯片的电路板可以包括在具有第一间距的第一触点的电路板的表面上的第一互连区域和围绕第一区域的第二互连区域，具有第二触点或迹线 第二间距小于第一间距。 第一个触点可以具有用于直接芯片附接（DCA）到集成电路芯片的设计规则（DR）。 可以通过将具有第一触点的牺牲衬底接合到板的表面来形成第一触点; 或通过激光划线沟槽，其中导体将被电镀以产生第一触点。 这样的板允许DCA的小尺寸处理器芯片用于诸如平板电脑，手机，智能电话和价值电话设备的设备。

公开(公告)号：US20150084051A1

公开(公告)日：2015-03-26

申请号：US14493877

申请日：2014-09-23

Applicant: Renesas Electronics Corporation

Inventor： Mitsuyuki Kubo ,  Junichi Yamada ,  Hiroshi Homma

IPC: H01L21/66 ,  G01R31/26 ,  G01R1/04 ,  H01L23/495

CPC classification number: H05K1/181 ,  G01R1/0408 ,  H01L22/14 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/642 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H05K1/0231 ,  H05K1/0268 ,  H05K1/115 ,  H05K1/141 ,  H05K3/3415 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Electrical characteristics of a mounting board over which a semiconductor device is mounted is improved. A mounting board (wiring board) includes a plurality of first through holes and second through holes extending from its upper surface bearing a semiconductor device (semiconductor package) to its lower surface and through-hole wirings formed in the respective through holes. The mounting board has a capacitor arranged on its lower surface and electrically connected with the semiconductor device via second electrodes. Among a plurality of first electrodes formed on the upper surface of the mounting board, the several first electrodes to be connected with the capacitor are connected with one wiring formed in a first through hole with a larger diameter than a signal transmission path.

公开(公告)号：US20150055312A1

公开(公告)日：2015-02-26

申请号：US14250965

申请日：2014-04-11

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Jeong Ho LEE ,  Mi Jin PARK ,  Chang Bae LEE ,  Young Do KWEON

IPC: H05K1/11 ,  H05K13/04 ,  H05K3/10 ,  B23K1/00 ,  H05K1/18 ,  H05K3/18

CPC classification number: B23K1/0016 ,  B23K2101/42 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/381 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/041

Abstract: Disclosed herein is an interposer substrate, including: a core layer and a through core via (TCV) penetrating through the core layer; circuit wirings formed on both surfaces of the core layer and a TCV upper pad and a TCV lower pad which are each bonded to upper and lower surfaces of the TCV formed on both surfaces of the core layer; upper insulating layers covering the TCV upper pad and the circuit wiring formed on one surface of the core layer and having the circuit wirings formed on upper surfaces thereof; a stack via penetrating through the upper insulating layers of each layer and having one end connected to the TCV upper pad; and a lower insulating layer covering the TCV lower pad and the circuit wiring formed on the other surface of the core layer and provided with an opening which exposes the TCV lower pad.

Abstract translation: 本发明公开了一种内插衬底，包括：穿透核心层的核心层和穿芯通孔（TCV）; 形成在芯层的两个表面上的电路布线和TCV上焊盘和TCV下焊盘，其各自结合到形成在芯层的两个表面上的TCV的上表面和下表面; 覆盖TCV上焊盘的上绝缘层和形成在芯层的一个表面上并且在其上表面上形成电路布线的电路布线; 通过穿过每层的上绝缘层并且具有连接到TCV上垫的一端的叠层; 以及覆盖TCV下焊盘的下绝缘层和形成在芯层的另一表面上的电路布线，并且设置有暴露TCV下焊盘的开口。

公开(公告)号：US08942005B2

公开(公告)日：2015-01-27

申请号：US12470311

申请日：2009-05-21

Applicant: Chris E. Geswender

Inventor： Chris E. Geswender

IPC: H05K1/11 ,  H05K1/14 ,  H05K7/02 ,  H05K7/04 ,  H05K7/18 ,  F42B15/08 ,  F42B30/00 ,  F42C19/06 ,  H05K7/14

CPC classification number: H05K1/144 ,  F42B15/08 ,  F42B30/006 ,  F42C19/06 ,  H05K7/1434 ,  H05K2201/09027 ,  H05K2201/10378 ,  H05K2201/2018

Abstract: An electronics module is provided for utilization onboard an airborne object. In one embodiment, the electronics module includes a housing having a cavity therein, a first printed circuit board (PCB) disposed in the cavity, a second PCB disposed in the cavity above the first PCB, and a supportive interconnect structure. The supportive interconnect structure includes a substantially annular insulative body and a plurality of vias. The substantially annular insulative body extends around an inner circumferential portion of the housing between the first PCB and the second PCB to support the second PCB and to axially space the second PCB from the first PCB. The plurality of vias is formed through the substantially annular insulative body and electrically couples the first PCB to the second PCB.

Abstract translation: 提供电子模块用于机载物体上的利用。 在一个实施例中，电子模块包括其中具有空腔的壳体，设置在空腔中的第一印刷电路板（PCB），布置在第一PCB上方的空腔中的第二PCB以及支撑互连结构。 支撑互连结构包括基本环形的绝缘体和多个通孔。 基本上环形的绝缘体围绕第一PCB和第二PCB之间的壳体的内圆周部分延伸以支撑第二PCB并使第二PCB从第一PCB轴向空间。 多个通孔通过大体上环形的绝缘体形成，并将第一PCB电耦合到第二PCB。

公开(公告)号：US08922234B2

公开(公告)日：2014-12-30

申请号：US14067685

申请日：2013-10-30

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Akinori Shiraishi ,  Hideaki Sakaguchi ,  Mitsutoshi Higashi

IPC: G01R31/00 ,  G01R1/073 ,  H05K3/40

CPC classification number: G01R1/07307 ,  G01R1/07314 ,  G01R1/0735 ,  G01R1/07364 ,  H05K3/4007 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/10378 ,  H05K2203/1572 ,  Y10T29/49155

Abstract: A probe card for conducting an electrical test on a test subject includes a substrate body including a first surface, which faces toward the test subject, and a second surface, which is opposite to the first surface. A through electrode extends through the substrate body between the first surface and the second surface. A contact bump is formed in correspondence with the electrode pad and electrically connected to the through electrode. An elastic body is filled in an accommodating portion, which is formed in the substrate body extending from the first surface toward the second surface. The contact bump is formed on the elastic body.

Abstract translation: 用于对受试对象进行电气测试的探针卡包括：衬底主体，包括朝向被测试对象的第一表面;以及与第一表面相对的第二表面。 通孔在第一表面和第二表面之间延伸穿过基底本体。 与电极焊盘对应地形成接触凸块，并且电连接到贯通电极。 弹性体填充在容纳部分中，该容纳部分形成在从第一表面向第二表面延伸的基底主体中。 接触凸块形成在弹性体上。

公开(公告)号：US08908384B2

公开(公告)日：2014-12-09

申请号：US13491378

申请日：2012-06-07

Applicant: Morgan Johnson ,  Frederick G. Weiss

Inventor： Morgan Johnson ,  Frederick G. Weiss

IPC: H05K7/00 ,  H05K1/02 ,  H01L23/32 ,  G06F1/32 ,  H05K1/18 ,  H05K1/14

CPC classification number: G06F13/16 ,  G06F1/32 ,  G06F13/4068 ,  G11C5/04 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K1/147 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/095 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10522 ,  Y02D10/151 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A computing device has a motherboard circuit substrate having at least one layer of electrical interconnects and a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the layer of electrical interconnects, wherein the circuit substrate has no memory interconnects.

Abstract translation: 计算设备具有具有至少一层电互连层的母板电路基板和布置成接收用于计算设备的主处理器的插座，该插座电耦合到电互连层的至少一部分，其中电路基板 没有内存互连。

公开(公告)号：US20140356635A1

公开(公告)日：2014-12-04

申请号：US13967186

申请日：2013-08-14

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim

IPC: H05K1/02 ,  H05K3/44

CPC classification number: H05K1/0271 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L2224/131 ,  H01L2224/16165 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/3511 ,  H05K1/0306 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/068 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T428/31678 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first core layer, a second core layer laterally located to the first core layer in the substrate, a first inorganic core layer (e.g., glass, silicon, ceramic) laterally positioned between the first core layer and the second core layer, the first inorganic core layer configured to be vertically aligned with a die configured to be coupled to the substrate, and a dielectric layer covering the first core layer, the second core layer and the first inorganic core layer. In some implementations, the first inorganic core layer has a first coefficient of thermal expansion (CTE), the die has a second coefficient of thermal expansion, and the first core layer has a third coefficient of thermal expansion (CTE). The first CTE of the first inorganic core layer closely matches the second CTE of the die in order to reduce the likelihood of warpage.

Abstract translation: 一些新颖特征涉及一种衬底，其包括第一芯层，横向位于衬底中的第一芯层的第二芯层，侧向位于第一芯层之间的第一无机芯层（例如，玻璃，硅，陶瓷） 和第二芯层，被配置为与被配置为耦合到基板的管芯垂直对准的第一无机芯层，以及覆盖第一芯层，第二芯层和第一无机芯层的电介质层。 在一些实施方案中，第一无机核心层具有第一热膨胀系数（CTE），所述管芯具有第二热膨胀系数，并且所述第一核心层具有第三热膨胀系数（CTE）。 第一无机芯层的第一CTE与模具的第二CTE紧密匹配，以减少翘曲的可能性。

公开(公告)号：US20140321087A1

公开(公告)日：2014-10-30

申请号：US13870644

申请日：2013-04-25

Applicant: Qinglei Zhang

Inventor： Qinglei Zhang

IPC: H05K1/09 ,  H05K3/24

CPC classification number: H05K3/244 ,  H01L21/4857 ,  H01L23/13 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81801 ,  H01L2924/12042 ,  H05K3/282 ,  H05K3/3436 ,  H05K2201/0376 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/025 ,  H05K2203/1476 ,  H05K2203/1572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于双表面光洁度封装衬底组件的技术和构造。 在一个实施例中，一种方法包括在位于封装衬底的第一侧上的一个或多个电路径特征上以及位于封装衬底的第二侧上的一个或多个焊盘上沉积第一表面光洁度，第二面与第一 侧面。 该方法还可以包括去除封装衬底的第一侧上的第一表面光洁度; 以及在第一侧的一个或多个电路径特征上沉积第二表面光洁度。 第二表面光洁度的沉积可以通过直接浸入金（DIG）工艺或有机可焊性防腐剂（OSP）工艺之一来完成。 可以描述和/或要求保护其他实施例。