公开(公告)号：US09689559B2

公开(公告)日：2017-06-27

申请号：US14665297

申请日：2015-03-23

Applicant: EDISON OPTO CORPORATION

Inventor： Hao Yun Chang ,  Yao-Chuan Hung

IPC: F21V19/00 ,  F21V9/16 ,  F21V23/06 ,  F21K9/232 ,  F21K9/27 ,  H05K1/18 ,  H01L25/075 ,  F21Y103/10 ,  F21Y115/10 ,  F21Y107/00

CPC classification number: F21V19/003 ,  F21K9/232 ,  F21K9/27 ,  F21V9/30 ,  F21V19/005 ,  F21V23/06 ,  F21Y2103/10 ,  F21Y2107/00 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L2224/48137 ,  H05K1/181 ,  H05K2201/09072 ,  H05K2201/10106 ,  H05K2201/1053

Abstract: An LED light core structure, which has better mechanical strength and good heat dissipation effect and is able to 360-degree project light. The LED light core structure includes a substrate having at least two faces. The substrate is formed with at least one opening communicating the two faces. LEDs are disposed on at least one of the two faces of the substrate at the opening, whereby the light emitted from the LEDs disposed on one of the two faces of the substrate can be projected through the opening to the opposite face of the substrate. Accordingly, the substrate can be made of metal material, whereby the substrate is unlikely to crack so that the ratio of good products is increased and the substrate can provide excellent heat dissipation effect for the LEDs. The conventional wolfram filament electrodes can be directly replaced with the LED light core structure.

公开(公告)号：US20170103932A1

公开(公告)日：2017-04-13

申请号：US15126172

申请日：2015-03-12

Applicant: SHIN-ETSU CHEMICAL CO., LTD.

Inventor： Katsuya TAKEMURA ,  Kyoko SOGA ,  Satoshi ASAI ,  Kazunori KONDO ,  Michihiro SUGO ,  Hideto KATO

IPC: H01L23/12 ,  C23C14/34 ,  C23C14/58 ,  C25D3/60 ,  C25D7/12 ,  C25D5/02 ,  C25D5/54 ,  C25D5/48 ,  B23K1/00 ,  H01L21/02 ,  B29C70/88 ,  B29C70/78 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  C23C14/04

CPC classification number: H01L23/12 ,  B23K1/0016 ,  B29C70/78 ,  B29C70/882 ,  B29K2063/00 ,  B29K2083/00 ,  B29K2105/20 ,  B29K2995/0005 ,  B29L2031/3493 ,  C23C14/042 ,  C23C14/34 ,  C23C14/58 ,  C25D3/60 ,  C25D5/022 ,  C25D5/48 ,  C25D5/505 ,  C25D5/54 ,  C25D7/00 ,  C25D7/123 ,  H01L21/02282 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  H01L2224/19 ,  H01L2224/83005

Abstract: A semiconductor apparatus includes a semiconductor device, on-semiconductor-device metal pad and metal interconnect each electrically connected to the semiconductor device, a through electrode and a solder bump each electrically connected to the metal interconnect, a first insulating layer on which the semiconductor device is placed, a second insulating layer formed on the semiconductor device, a third insulating layer formed on the second layer. The metal interconnect is electrically connected to the semiconductor device via the on-semiconductor-device metal pad at an upper surface of the second layer, penetrates the second layer from its upper surface, and is electrically connected to the through electrode at an lower surface of the second layer, and an under-semiconductor-device metal interconnect is between the first layer and the semiconductor device, and the under-semiconductor-device metal interconnect is electrically connected to the metal interconnect at the lower surface of the second layer.

公开(公告)号：US09460938B2

公开(公告)日：2016-10-04

申请号：US14254805

申请日：2014-04-16

Applicant: Renesas Electronics Corporation

Inventor： Hiroyasu Miyamoto

IPC: H01L23/12 ,  H01L21/56 ,  H01L23/544 ,  H01L23/10 ,  H01L25/065 ,  H01L25/18 ,  H01L23/04 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L23/50 ,  H05K1/02

CPC classification number: H01L21/563 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/544 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/5442 ,  H01L2223/54486 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/3701 ,  H01L2224/37012 ,  H01L2224/37147 ,  H01L2224/376 ,  H01L2224/40225 ,  H01L2224/40499 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/73263 ,  H01L2224/83132 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/84132 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/16196 ,  H01L2924/16251 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/0203 ,  H05K2201/066 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/1056 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07811

Abstract: The long sides of a rectangular control chip and the long sides of a rectangular memory chip are arranged parallel with first sides of the upper surface of a wiring substrate in a BGA. A lid includes a pair of first brims and a pair of second brims, the widths of the second brims are formed wider than those of the first brims, and a mounting area for mounting chip parts and a junction base area for joining the lid are secured outside the short sides of the control chip mounted on the upper surface of the wiring substrate and outside the short sides of the memory chip mounted on the upper surface of the wiring substrate, which enables the wide-width second brims of the lid to be disposed on the junction base area. Hence, the mounting area of the BGA can be reduced.

Abstract translation: 矩形控制芯片的长边和矩形存储芯片的长边与布线基板的上表面的第一侧平行布置在BGA中。 盖子包括一对第一边缘和一对第二边缘，第二边缘的宽度形成得比第一边缘的宽度宽，并且用于安装芯片部分的安装区域和用于接合盖子的接合基座区域被固定 在安装在布线基板的上表面上的控制芯片的短边外部以及安装在布线基板的上表面上的存储芯片的短边外侧，能够布置盖的宽幅第二边缘 在交汇处基地区。 因此，可以减小BGA的安装面积。

公开(公告)号：US20160284633A1

公开(公告)日：2016-09-29

申请号：US15174208

申请日：2016-06-06

Applicant: International Business Machines Corporation

Inventor： Ai Kiar Ang ,  Michael Lauri

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H05K1/11 ,  H01L21/4839 ,  H01L23/49537 ,  H01L23/49555 ,  H01L23/49565 ,  H01L23/49575 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/1029 ,  H01L2924/181 ,  H05K1/0313 ,  H05K1/144 ,  H05K1/18 ,  H05K1/181 ,  H05K3/328 ,  H05K3/341 ,  H05K3/3421 ,  H05K3/3426 ,  H05K2201/10015 ,  H05K2201/10227 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10962 ,  Y02P70/613 ,  H01L2924/00012

Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.

公开(公告)号：US20160268050A1

公开(公告)日：2016-09-15

申请号：US15042236

申请日：2016-02-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuo HATTORI ,  Isamu FUJIMOTO ,  Shinichiro KUROIWA

IPC: H01G4/40 ,  H01C1/14 ,  H01C1/012 ,  H05K1/18

CPC classification number: H01G4/40 ,  H01C1/012 ,  H01C1/14 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1053 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A composite electronic component includes a capacitor and a resistor stacked in a height direction. The capacitor includes a capacitor body, and first and second external electrodes. The resistor includes a base portion, a resistor, first and second upper surface conductors, first and second lower surface conductors, first connecting conductors, and second connecting conductors. An upper surface of the base portion of the resistor faces a lower surface of the capacitor body of the capacitor, and the first upper surface conductor and the first external electrode are electrically connected, and the second upper surface conductor and the second external electrode are electrically connected.

Abstract translation: 复合电子部件包括在高度方向上堆叠的电容器和电阻器。 电容器包括电容器主体，以及第一和第二外部电极。 电阻器包括基部，电阻器，第一和第二上表面导体，第一和第二下表面导体，第一连接导体和第二连接导体。 电阻器的基部的上表面面对电容器的电容器主体的下表面，并且第一上表面导体和第一外部电极电连接，第二上表面导体和第二外部电极是电气的 连接的。

公开(公告)号：US09440601B2

公开(公告)日：2016-09-13

申请号：US14230678

申请日：2014-03-31

Applicant: Johnson Controls Technology Company

Inventor： Edward J. Soleski ,  Mikhail S. Balk ,  Lisa L. Winders ,  Richard M. DeKeuster ,  John P. Dinkelman

IPC: H01M10/48 ,  B60R16/03 ,  H02J7/00 ,  G01R31/36 ,  H01M10/04 ,  H01M10/42 ,  H01M10/058 ,  H01M2/24 ,  H01M2/20 ,  H01M2/34 ,  H01H47/32 ,  H05K1/18 ,  H05K3/32 ,  B60L11/18 ,  H01M2/12 ,  H01M2/10 ,  H01R12/71 ,  H05K1/02 ,  H02H7/18 ,  G01R31/02

CPC classification number: H01M2/22 ,  B60L1/003 ,  B60L1/02 ,  B60L1/14 ,  B60L3/0046 ,  B60L3/12 ,  B60L11/123 ,  B60L11/14 ,  B60L11/1803 ,  B60L11/1851 ,  B60L11/1861 ,  B60L11/1864 ,  B60L11/1874 ,  B60L11/1877 ,  B60L11/1879 ,  B60L15/20 ,  B60L2210/10 ,  B60L2210/40 ,  B60L2240/34 ,  B60L2240/545 ,  B60L2240/547 ,  B60L2240/549 ,  B60L2250/10 ,  B60L2260/26 ,  B60L2270/20 ,  B60R16/03 ,  B60R16/033 ,  G01R31/025 ,  G01R31/362 ,  G01R31/3627 ,  H01H47/325 ,  H01M2/1077 ,  H01M2/1205 ,  H01M2/1211 ,  H01M2/1252 ,  H01M2/20 ,  H01M2/206 ,  H01M2/24 ,  H01M2/305 ,  H01M2/32 ,  H01M2/34 ,  H01M2/342 ,  H01M4/661 ,  H01M4/665 ,  H01M10/04 ,  H01M10/0413 ,  H01M10/058 ,  H01M10/425 ,  H01M10/4257 ,  H01M10/482 ,  H01M10/486 ,  H01M10/6551 ,  H01M2010/4271 ,  H01M2010/4278 ,  H01M2200/103 ,  H01M2220/20 ,  H01M2250/20 ,  H01R12/716 ,  H02H7/18 ,  H02J7/0021 ,  H02J7/0063 ,  H05K1/0262 ,  H05K1/0263 ,  H05K1/18 ,  H05K3/32 ,  H05K2201/10492 ,  H05K2201/1053 ,  H05K2201/10545 ,  Y02T10/6217 ,  Y02T10/645 ,  Y02T10/7005 ,  Y02T10/7016 ,  Y02T10/7044 ,  Y02T10/705 ,  Y02T10/7061 ,  Y02T10/7077 ,  Y02T10/7216 ,  Y02T10/7241 ,  Y02T10/7275 ,  Y10T29/49108 ,  Y10T29/4911 ,  Y10T29/49114

Abstract: A battery module and a method of manufacture are provided. The battery module may include a printed circuit board (PCB) assembly. The PCB assembly may include a PCB designed to be disposed in a battery module for controlling operations of the battery module. The PCB may also include voltage sensing circuitry. In addition, the PCB assembly may include a bus bar cell interconnect. The bus bar cell interconnect may electrically couple batteries of the battery module. The PCB assembly may also include a voltage sense connection tab. The voltage sense connection tab may carry a voltage between a bus bar cell interconnect of the battery module and the voltage sensing circuitry on the PCB.

Abstract translation: 提供电池模块和制造方法。 电池模块可以包括印刷电路板（PCB）组件。 PCB组件可以包括设计成设置在电池模块中以控制电池模块的操作的PCB。 PCB还可以包括电压感测电路。 此外，PCB组件可以包括汇流条单元互连。 母线电池互连可以电连接电池模块的电池。 PCB组件还可以包括电压感测连接片。 电压感测连接片可以在电池模块的汇流条单元互连和PCB上的电压感测电路之间承载电压。

公开(公告)号：US20160219689A1

公开(公告)日：2016-07-28

申请号：US15091564

申请日：2016-04-05

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hideyo NAKAMURA ,  Masafumi HORIO

IPC: H05K1/02 ,  H05K1/03 ,  H01L25/065 ,  H05K1/18

CPC classification number: H05K1/025 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/73265 ,  H02M7/003 ,  H02M7/487 ,  H05K1/0306 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2201/1053 ,  H01L2924/00014

Abstract: A semiconductor device includes a first circuit board on which a first switching element and a first diode connected in inverse parallel are mounted, a second circuit board on which a second switching element and a second diode connected in inverse parallel are mounted, a printed circuit board disposed opposite the first circuit board and the second circuit board, and a plurality of conductive posts which electrically connect the first switching element, the second switching element, the first diode, the second diode, the first circuit board, or the second circuit board and metal layers of the printed circuit board. The first switching element and the second switching element are connected in anti-series to form a bidirectional switch.

Abstract translation: 一种半导体器件包括：第一电路板，其上安装有逆并联连接的第一开关元件和第一二极管;第二电路板，其上安装有并联连接的第二开关元件和第二二极管，印刷电路板 与第一电路板和第二电路板相对设置的多个导电柱，将第一开关元件，第二开关元件，第一二极管，第二二极管，第一电路板或第二电路板电连接的多个导电柱，以及 印刷电路板的金属层。 第一开关元件和第二开关元件反串联连接以形成双向开关。

公开(公告)号：US09398683B2

公开(公告)日：2016-07-19

申请号：US13850756

申请日：2013-03-26

Applicant: Apple Inc.

Inventor： David Fifield

IPC: H01G4/228 ,  H05K1/02 ,  H01G4/38 ,  H01G4/40 ,  H01G4/012 ,  H05K1/18

CPC classification number: H05K1/0239 ,  H01G4/012 ,  H01G4/228 ,  H01G4/385 ,  H01G4/40 ,  H05K1/0233 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y02P70/611

Abstract: A packaged capacitor component such as a surface mount technology capacitor component may be formed with multiple self-resonant frequencies. The capacitor component may include multiple capacitor portions separated by dielectric layers. The capacitor portions may each be formed from interleaving conductive layers. Additional dielectric layers may be interposed between the interleaving conductive layers. Each capacitor portion may be characterized by a corresponding self-resonance frequency. If desired, a packaged capacitor component having multiple self-resonant frequencies may be formed by stacking multiple surface-mount capacitor components. Each of the stacked surface-mount capacitor components may include interleaving conductive layers that are centered between top and bottom surfaces of that component. Packaged capacitor components having multiple self-resonance frequencies may be used as direct-current blocking capacitors or decoupling capacitors.

Abstract translation: 可以形成具有多个自谐振频率的诸如表面贴装技术电容器部件的封装的电容器部件。 电容器组件可以包括由电介质层分离的多个电容器部分。 电容器部分可以分别由交织导电层形成。 另外的电介质层可插入交织导电层之间。 每个电容器部分的特征在于相应的自谐振频率。 如果需要，可以通过堆叠多个表面贴装电容器部件来形成具有多个自谐振频率的封装电容器部件。 层叠的表面安装电容器组件中的每一个可以包括在该部件的顶表面和底表面之间居中的交错导电层。 具有多个自谐振频率的封装电容器组件可以用作直流阻塞电容器或去耦电容器。

公开(公告)号：US20160057860A1

公开(公告)日：2016-02-25

申请号：US14462721

申请日：2014-08-19

Applicant: International Business Machines Corporation

Inventor： Layne A. Berge ,  John R. Dangler ,  Matthew S. Doyle ,  Jesse Hefner

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/14 ,  B23K1/00 ,  H05K3/34

CPC classification number: H05K1/14 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/19 ,  B23K3/047 ,  B23K3/087 ,  B23K2101/42 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2203/0278 ,  Y02P70/611

Abstract: An electrical connection is established between a first electrical component and a second electrical component of an assembly and a compression tool is used to apply a compression force to the assembly. The assembly also includes a metallized particle interconnect (MPI) between the first electrical component and the second electrical component and solder components outside a boundary of the MPI and extending from the first electrical component to the second electrical component. The solder components are melted by applying heat to the assembly. The solder components are solidified by cooling the assembly and the compression tool is removed.

Abstract translation: 在组件的第一电气部件和第二电气部件之间建立电连接，并且使用压缩工具将压缩力施加到组件。 组件还包括在第一电气部件和第二电气部件之间的金属化颗粒互连（MPI）以及在MPI的边界外部并从第一电气部件延伸到第二电气部件的焊接部件。 通过向组件施加热量来熔化焊料组分。 焊接部件通过冷却组件而固化，并且去除压缩工具。

公开(公告)号：US09258890B2

公开(公告)日：2016-02-09

申请号：US14294875

申请日：2014-06-03

Applicant: STMicroelectronics, Inc.

Inventor： Rammil Seguido ,  Frederick Ray Gomez ,  Emmanuel Angeles

IPC: H01L23/52 ,  H01L23/48 ,  H05K1/02 ,  H05K3/30 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0296 ,  H01L23/66 ,  H01L25/0652 ,  H01L2224/48091 ,  H01L2224/73265 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/09236 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10719 ,  H05K2201/10977 ,  H05K2203/049 ,  Y10T29/49146 ,  H01L2924/00014

Abstract: Delamination of stacked integrated circuit die configurations on printed circuit boards is avoided by providing a metal trace support structure underneath the die stack. The metal trace support structure features substantially equally spaced thin metal traces in place of a contiguous metal plate which has been used in the past. Spaced apart thin metal traces are less vulnerable to thermal expansion than a metal plate which has a large thermal mass. The metal traces still provide structural stability, while preventing delamination of the die stack configuration during thermal processing. A method of attaching a bridge die stack configuration to a printed circuit board by adhering a die attach film to a field of metal traces is demonstrated. In addition, the electrical and structural integrity of the bridge die stack formed with a metal trace support structure is confirmed with test results.

Abstract translation: 通过在管芯堆叠下方提供金属迹线支撑结构，可以避免印刷电路板上的堆叠集成电路管芯结构的分层。 金属迹线支撑结构具有基本相等间隔的细金属迹线，代替过去使用的连续金属板。 分隔开的薄金属迹线比具有大热质量的金属板不易受热膨胀。 金属迹线仍然提供结构稳定性，同时防止热处理期间芯片堆叠配置的分层。 证明了通过将管芯附着膜粘附到金属痕迹的领域将桥模组叠构造附着到印刷电路板的方法。 此外，用测试结果证实了由金属迹线支撑结构形成的桥模组的电气和结构完整性。