公开(公告)号：US20030076197A1

公开(公告)日：2003-04-24

申请号：US10001781

申请日：2001-10-24

Inventor： Istvan Novak ,  Valerie St.Cyr ,  Michael C. Freda ,  Merle Tetreault

IPC: H01P005/12

CPC classification number: H05K1/0234 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K1/167 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611

Abstract: A method for achieving a desired value of electrical impedance between conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the conductors. The resistance elements may be annular resistors, and may provide the designer a greater degree of control of the system ESR. The annular resistors may comprise a first terminal, an annular resistor, and a second terminal. The second terminal may be located within the confines of the annular resistor. The annular resistors may be printed onto a conductive plane (e.g. a power plane or a ground plane), or may be a discrete component.

Abstract translation: 一种用于通过电耦合多个旁路电容器和在导体之间串联的对应的电阻元件来实现电力分配结构的导体之间的电阻抗的期望值的方法。 电阻元件可以是环形电阻器，并且可以向设计者提供对系统ESR的更大程度的控制。 环形电阻器可以包括第一端子，环形电阻器和第二端子。 第二端子可以位于环形电阻器的范围内。 环形电阻器可以印刷到导电平面（例如电源平面或接地平面）上，或者可以是分立的部件。

公开(公告)号：US20030063417A1

公开(公告)日：2003-04-03

申请号：US09967763

申请日：2001-09-29

Inventor： Robert A. Pereira ,  D. Joseph Stoddard

IPC: H01G002/12

CPC classification number: H05K1/0201 ,  H05K1/0231 ,  H05K1/114 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A method for mounting a component on an assembly is provided, such as to prevent shorting between a voltage plane and a ground plane that may be caused when the component fails and generates temperature rises that result in insulation failure. The method includes removing a section of one or more of the group including a ground plane and a voltage plane in an area of the component, where the area of the section is selected to prevent damage to the component that can be caused by shorting between the ground plane and the voltage plane if insulation failure occurs.

Abstract translation: 提供了一种用于将组件安装在组件上的方法，以防止在组件故障时可能引起的电压平面和接地面之间的短路，并产生导致绝缘失效的温度上升。 该方法包括在组件的区域中去除包括接地平面和电压平面的该组中的一个或多个的部分，其中选择该部分的区域以防止可能由于部件之间的短路而导致的部件损坏 如果发生绝缘故障，接地层和电压平面。

公开(公告)号：US20030021097A1

公开(公告)日：2003-01-30

申请号：US10101098

申请日：2002-03-20

Inventor： Hideo Kikuchi ,  Toshiyuki Kaneko ,  Hideki Kikuchi ,  Kazuhiro Kinoshita ,  Kiyohiko Kaiya ,  Yutaka Akimoto

IPC: H05K009/00

CPC classification number: H05K1/182 ,  H01R13/6471 ,  H05K1/0218 ,  H05K1/0243 ,  H05K2201/093 ,  H05K2201/09354 ,  H05K2201/09809 ,  H05K2201/10356

Abstract: Occurrence of EMI is reduced without a sharp increase of the manufacturing cost by suppressing a common mode current stably. There is provided a disclosed printed-circuit board being adapted such that a width of an outer edge section of a T-shaped pattern is widened so as to surround a recessed section with a frame-shaped additional electric conductor by electrically connecting the frame-shaped additional electric conductor with the T-shaped pattern making up a ground pattern so as to close the recessed section.

Abstract translation: 通过稳定地抑制共模电流，可以降低EMI的发生，而不会大大提高制造成本。 提供了一种公开的印刷电路板，其适于使得T形图案的外边缘部分的宽度被加宽，以便通过将框架形附加导电体电连接 具有T形图案的附加电导体构成接地图案，以闭合凹部。

公开(公告)号：US20020118526A1

公开(公告)日：2002-08-29

申请号：US09860653

申请日：2001-05-18

Inventor： Gregory J. Fritz ,  Alejandra Anderson ,  Robin Berg ,  Todd Husom ,  Eric Sit

IPC: H05K007/14

CPC classification number: H05K7/1425 ,  H04Q1/03 ,  H04Q1/035 ,  H04Q1/10 ,  H04Q1/116 ,  H04Q2201/06 ,  H04Q2201/10 ,  H04Q2201/12 ,  H05K1/0216 ,  H05K1/14 ,  H05K1/18 ,  H05K7/186 ,  H05K2201/044 ,  H05K2201/093 ,  H05K2201/09354 ,  H05K2201/09663

Abstract: A chassis and associated telecommunication circuit card are disclosed. The chassis has heat dissipation and flame containment features while accommodating a high density of the circuitry cards. Embodiments include an inner housing with a double-layer middle floor dividing the chassis into top and bottom chambers. Each layer has partially aligned slots, and an air gap is provided between the two layers. Embodiments also include a double-layer mesh cover with an air gap existing between the two mesh layers. Projections and grooves are provided on the inner surfaces of the inner housing to receive circuit cards having a guide on one edge and a fin on another. The circuit card includes conductor structures such as multiple board layers with paired and segregated conductors. The circuit card also includes some components positioned to cooperate with the ventilation features of the chassis and includes some components chosen for low-power consumption or reduced flammability.

Abstract translation: 公开了一种底盘和相关通信电路卡。 底盘具有散热和阻燃特征，同时容纳高密度的电路卡。 实施例包括具有双层中间层的内壳，其将底盘分成顶部和底部室。 每个层具有部分对准的槽，并且在两层之间提供气隙。 实施例还包括在两个网格层之间具有气隙的双层网状覆盖物。 在内壳体的内表面上设置突起和凹槽，以接收在一个边缘上具有引导件的电路卡和另一边缘上的翅片。 电路卡包括导体结构，例如具有配对和分离的导体的多个板层。 电路卡还包括定位成与底盘的通风特征配合的一些组件，并且包括一些选择用于低功耗或降低可燃性的组件。

公开(公告)号：US20020118524A1

公开(公告)日：2002-08-29

申请号：US09795656

申请日：2001-02-28

Inventor： Robin Berg JR. ,  Todd Husom ,  Derek Sayres

IPC: H05K007/14

CPC classification number: H05K7/1425 ,  H04Q1/023 ,  H04Q1/03 ,  H04Q1/035 ,  H04Q1/116 ,  H04Q1/155 ,  H04Q2201/06 ,  H04Q2201/10 ,  H04Q2201/12 ,  H05K1/0216 ,  H05K1/14 ,  H05K2201/093 ,  H05K2201/09663

Abstract: A chassis and associated telecommunication circuit card are disclosed. The chassis has heat dissipation and flame containment features while accommodating a high density of the circuitry cards. Embodiments include an inner housing with a double-layer middle floor dividing the chassis into top and bottom chambers. Each layer has partially aligned slots, and an air gap is provided between the two layers. Embodiments also include a double-layer mesh cover with an air gap existing between the two mesh layers. Projections and grooves are provided on the inner surfaces of the inner housing to receive circuit cards having a guide on one edge and a fin on another. The guide includes an opening that at least partially aligns with slots on the adjacent surface of the inner housing. The circuit card includes a finger extending from a faceplate that facilitates insertion and removal of the circuit card relative to the chassis.

Abstract translation: 公开了一种底盘和相关通信电路卡。 底盘具有散热和阻燃特征，同时容纳高密度的电路卡。 实施例包括具有双层中间层的内壳，其将底盘分成顶部和底部室。 每个层具有部分对准的槽，并且在两层之间提供气隙。 实施例还包括在两个网格层之间具有气隙的双层网状覆盖物。 在内壳体的内表面上设置突起和凹槽，以接收在一个边缘上具有引导件的电路卡和另一边缘上的翅片。 引导件包括至少部分地与内壳体的相邻表面上的狭槽对准的开口。 电路卡包括从面板延伸的手指，其有助于电路卡相对于底盘的插入和移除。

公开(公告)号：US06418032B2

公开(公告)日：2002-07-09

申请号：US09800582

申请日：2001-03-08

Applicant: Masayuki Hirata ,  Osamu Ueno

Inventor： Masayuki Hirata ,  Osamu Ueno

IPC: H05K111

CPC classification number: H05K9/0039 ,  H05K1/0225 ,  H05K1/0233 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/1006 ,  H05K2201/10689

Abstract: A printed wiring board in which noise components at a high frequency side of a power supply voltage can be eliminated, and undesired radiation noisewhich is newly generated can be suppressed, such that noise can be greatly reduced overall. The printed wiring board includes a first signal layer, a GND layer, a power source layer and a second signal layer. A sub-power source layer is provided on a same layer as a main power source layer. The sub-power source layer is formed in a substantially oval shape at a predetermined position in a substantially oval opening in the main power source layer, such that it is not in direct contact with the main power source layer. Power supply voltage is supplied from the main power source layer through an L-type filter.

Abstract translation: 可以抑制能够消除电源电压的高频侧的噪声成分的新印刷布线板，并且可以抑制新生成的不期望的放射线，使得整体上可以大大降低噪声。 印刷电路板包括第一信号层，GND层，电源层和第二信号层。 子电源层设置在与主电源层相同的层上。 子电源层在主电源层中的大致椭圆形的开口中的预定位置处形成为大致椭圆形状，使得它不与主电源层直接接触。 电源电压由主电源层通过L型滤波器供电。

公开(公告)号：US06392301B1

公开(公告)日：2002-05-21

申请号：US09426394

申请日：1999-10-25

Applicant: Alex Waizman ,  Chee-Yee Chung ,  Bob Sankman

Inventor： Alex Waizman ,  Chee-Yee Chung ,  Bob Sankman

IPC: H01L2348

CPC classification number: H05K1/0253 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0224 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/093 ,  H05K2201/096 ,  H05K2201/09681 ,  H05K2201/10674 ,  H05K2203/1178 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T428/24917 ,  H01L2224/0401

Abstract: A semiconductor device package includes multiple build-up layers of metal sandwiching non-conductive layers. The metal layers include apertures, or degassing holes. A manual method and a computer-implemented method for designing the semiconductor device packages includes stepping polygons across a representation of a conductive layer. A signal routing layer that includes signal traces is then superimposed on the conductive layer. Signal traces overlap the polygons creating regions of intersection that can be enlarged. Regions of intersection are removed from the polygons and the remaining polygon area is designated as apertures in the conductive layer. A semiconductor device package and packaged integrated circuit includes apertures in a conductive layer such that the apertures generally form a radial pattern outward from a region on the package. Signal traces also traverse the package generally radially outward such that the traces and the apertures do not overlap. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by trace.

Abstract translation: 半导体器件封装包括金属夹层非导电层的多个堆积层。 金属层包括孔或脱气孔。 用于设计半导体器件封装的手动方法和计算机实现的方法包括穿过导电层的表示的步进多边形。 然后将包括信号迹线的信号路由层叠加在导电层上。 信号迹线与可以扩大的交叉点的多边形重叠。 从多边形去除交叉区域，剩余的多边形区域被指定为导电层中的孔。 半导体器件封装和封装的集成电路包括导电层中的孔，使得孔通常从封装上的区域向外形成径向图案。 信号迹线也通常径向向外穿过封装，使得迹线和孔不重叠。 阻抗变化由于通过痕迹通过或减少的脱气孔的数量减少而减小。

公开(公告)号：US06365839B1

公开(公告)日：2002-04-02

申请号：US09587307

申请日：2000-06-05

Applicant: Eric F. Robbins ,  Stephen W. Berry

Inventor： Eric F. Robbins ,  Stephen W. Berry

IPC: H05K103

CPC classification number: H05K1/0253 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09845 ,  H05K2201/09972

Abstract: A multi-layer printed circuit board provides at least two sections thereon. One section has a grouping of high-impedance traces and another adjacent section, separated by a dividing line, has a mainly low-impedance signal traces. The high-impedance section has at least one of a ground and power plane separated from a grouping of central layers, containing the high-impedance traces, by at least one empty or “void” layer. The void layer is likewise filled by the ground and power planes in the within low-impedance section by stepping the ground/power plane inwardly toward the central layers while providing another low-impedance signal trace in the layer above and below the respective ground and power planes. In a preferred embodiment there are at least nine layers of circuit board material with high-impedance traces on a central grouping of at least three central board layers with three layers disposed respectively above and below the central board layers.

Abstract translation: 多层印刷电路板在其上提供至少两个部分。 一个部分具有一组高阻抗迹线，另一个相邻部分由分割线分隔，具有主要的低阻抗信号迹线。 高阻抗部分具有通过至少一个空或“空”层与包含高阻抗迹线的一组中心层分离的接地层和功率平面中的至少一个。 同样，通过将接地/功率平面向内朝向中心层向内侧，通过在内部低阻抗部分内的接地层和电源平面填充空隙层，同时在相应的地面和功率上方和下方的层中提供另外的低阻抗信号迹线 飞机 在一个优选实施例中，至少有九层电路板材料在至少三个中心板层的中心组上具有高阻抗迹线，三层分别设置在中心板层的上方和下方。

公开(公告)号：US20020036099A1

公开(公告)日：2002-03-28

申请号：US09963640

申请日：2001-09-27

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shogo Hachiya

IPC: H05K001/03

CPC classification number: H05K1/0253 ,  H05K1/0298 ,  H05K1/111 ,  H05K2201/093 ,  H05K2201/0969

Abstract: A circuit card for transmitting signals having one or more long and narrow holes in a ground/power supply plane under a pad, which is connected to a pattern, the hole extending in a direction substantially parallel with a direction of the pattern extending away from the pad. The holes are sized and positioned to substantially minimize a mismatch of impedance between the pad and the pattern so that reflection of transmission signals caused by impedance mismatch can be suppressed.

Abstract translation: 一种电路卡，用于发送信号，该信号具有一个或多个长孔和细孔，该接地/电源平面在焊盘下面，该接地/电源平面连接到图案上，所述孔沿与所述图案的远离所述图案的方向基本平行的方向延伸 垫。 孔的尺寸和位置大致最小化焊盘和图案之间的阻抗失配，从而可以抑制由阻抗失配引起的传输信号的反射。

公开(公告)号：US06353540B1

公开(公告)日：2002-03-05

申请号：US08860181

申请日：1997-07-10

Applicant: Yutaka Akiba ,  Yasunori Narizuka ,  Hirayoshi Tanei ,  Naoya Kitamura

Inventor： Yutaka Akiba ,  Yasunori Narizuka ,  Hirayoshi Tanei ,  Naoya Kitamura

IPC: H05K116

CPC classification number: H05K1/0246 ,  H01L23/5383 ,  H01L23/552 ,  H01L25/16 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0227 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/092 ,  H05K1/113 ,  H05K1/115 ,  H05K1/162 ,  H05K1/167 ,  H05K3/403 ,  H05K3/4053 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/4652 ,  H05K3/467 ,  H05K9/0039 ,  H05K2201/0209 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09354 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/09663 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10045 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2224/0401

Abstract: A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation off a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure, a circuit board using it, and a method of manufacturing the circuit board are also disclosed. Parallel plate lines in which the Q-value of the stray capacitance between solid layers viewed from the power supply layer and ground layer is equivalently reduced and which are matchedly terminated by forming a structure in which a resistor (resistor layer) and another ground layer are provided in addition to the power supply layer and the ground layer on a multilayered circuit board. A closed shield structure is also disclosed. This invention can remarkably suppress unwanted radiation by absorbing the potential fluctuation (resonance) which occurs in a power supply loop by equivalently reducing the Q-value of the stray capacitance, absorbing the standing wave by the parallel plate lines matchedly terminated and, closing and shielding the parallel plate lines.

Abstract translation: 一种低EMI电路，其通过将电源层上的电位波动相对于在切换IC器件等而发生的接地层的电位变化转换为基底中的焦耳热，而不使用任何部件作为对策来实现高安装密度 针对EMI。 还公开了其结构，使用它的电路板以及制造电路板的方法。 从电源层和接地层观察的固体层之间的杂散电容的Q值的平行板线等效地减少，并且通过形成其中电阻器（电阻层）和另一接地层的结构匹配地终止 除了在多层电路板上的电源层和接地层之外提供。 还公开了封闭的屏蔽结构。 本发明通过吸收电源回路中发生的电位波动（谐振）可以显着地抑制不期望的辐射，通过等效地降低杂散电容的Q值，吸收平行板线匹配终止的驻波，闭合屏蔽 平行板线。