公开(公告)号：US20090071705A1

公开(公告)日：2009-03-19

申请号：US12007688

申请日：2008-01-14

Applicant: Moon-Il Kim ,  Young-Do Kweon

Inventor： Moon-Il Kim ,  Young-Do Kweon

IPC: H01R12/06 ,  H05K3/42

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/07802 ,  H01L2924/18162 ,  H05K2201/0367 ,  H05K2201/10159 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/0156 ,  H05K2203/1469 ,  Y10T29/4913 ,  Y10T29/49165 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/83005

Abstract: A PCB (printed circuit board) having embedded components and a method for manufacturing thereof are disclosed. The PCB may include a dielectric substrate having a cavity formed in one side, a first component inserted in the cavity such that an electrode of the first component faces the one side of the dielectric substrate, a second component mounted on one side of the first component such that an electrode of the second component faces the same direction as the electrode of the first component, a first dielectric layer formed on one side of the dielectric substrate such that the first dielectric layer covers the second component, and a second dielectric layer formed on the other side of the dielectric substrate such that the second dielectric layer covers the first component. In this PCB, multiple components of differing thickness can be mounted, and vias can be formed more easily.

Abstract translation: 公开了具有嵌入部件的PCB（印刷电路板）及其制造方法。 PCB可以包括具有在一侧形成的空腔的电介质基板，插入空腔中的第一部件，使得第一部件的电极面向电介质基板的一侧，第二部件安装在第一部件的一侧 使得第二部件的电极面向与第一部件的电极相同的方向，形成在电介质基板的一侧上的第一电介质层，使得第一电介质层覆盖第二部件，第二电介质层形成在 电介质基板的另一侧使得第二介电层覆盖第一部件。 在该PCB中，可以安装不同厚度的多个部件，并且可以更容易地形成通孔。

公开(公告)号：US20090051004A1

公开(公告)日：2009-02-26

申请号：US11844672

申请日：2007-08-24

Applicant: Weston C. Roth ,  James D. Jackson ,  Damion Searls ,  Kevin Byrd

Inventor： Weston C. Roth ,  James D. Jackson ,  Damion Searls ,  Kevin Byrd

IPC: H01L29/00 ,  H01L21/00 ,  H01L23/48

CPC classification number: H01L23/49816 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/145 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/10242 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: A microelectronic package and a method of forming the package. The package includes a first level package mounted to a carrier. The first level package includes a package substrate having a die side and a carrier side; and a microelectronic die mounted on the package substrate at the die side thereof. The carrier has a substrate side, and the first level package is mounted on the carrier at the substrate side thereof. A rigid body is attached to the carrier side of the substrate at an attachment location of the substrate and to the substrate side of the carrier at an attachment location of the carrier, the attachment location of the carrier being electrically unconnected, the rigid body being configured and disposed to provide structural support between the substrate and the carrier.

Abstract translation: 微电子封装和形成封装的方法。 该包装包括安装在载体上的第一级封装。 第一级封装包括具有裸片侧和载体侧的封装基板; 以及在其芯片侧安装在封装基板上的微电子管芯。 载体具有基板侧，并且第一级封装在其基板侧安装在载体上。 刚性体在基板的安装位置和载体的安装位置处附着到基板的载体侧，载体的附接位置电连接，刚体被构造成 并设置成在基板和载体之间提供结构支撑。

公开(公告)号：US20090016033A1

公开(公告)日：2009-01-15

申请号：US12136007

申请日：2008-06-09

Applicant: Seng Guan Chow ,  Il Kwon Shim ,  Byung Joon Han ,  Kambhampati Ramakrishna

Inventor： Seng Guan Chow ,  Il Kwon Shim ,  Byung Joon Han ,  Kambhampati Ramakrishna

IPC: H05K1/18

CPC classification number: H05K1/189 ,  H01L23/49816 ,  H01L23/5387 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H05K1/141 ,  H05K1/147 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/042 ,  H05K2201/056 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2203/1316 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099

Abstract: An integrated circuit package system includes: providing a flexible circuit substrate; mounting an integrated circuit or an integrated circuit package over the flexible circuit substrate and connected to the flexible circuit substrate with interconnects; and encapsulating the integrated circuit or integrated circuit package with a mounded encapsulation having a first level and a second level, the second level having the flexible circuit substrate folded thereover.

Abstract translation: 集成电路封装系统包括：提供柔性电路基板; 在柔性电路基板上安装集成电路或集成电路封装，并用互连连接到柔性电路基板; 以及用具有第一电平和第二电平的堆叠封装封装所述集成电路或集成电路封装，所述第二电平具有在其上折叠的所述柔性电路基板。

公开(公告)号：US20090001541A1

公开(公告)日：2009-01-01

申请号：US11824351

申请日：2007-06-29

Applicant: James B. Covert ,  David S. Trollope

Inventor： James B. Covert ,  David S. Trollope

IPC: H01L23/02 ,  H01L21/44

CPC classification number: H05K1/18 ,  H01L25/105 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/0002 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10704 ,  H01L2924/00

Abstract: Systems and methods for vertically stacking integrated circuit (IC) modules on a motherboard to conserve motherboard space and reduce power consumption are disclosed. IC modules can comprise processor circuitry, memory elements, communication circuitry, etc. Pins on each IC module can be directly inserted into lower IC module or into a socket layer that couples the IC modules. Heat generated by the IC modules can be dissipated by inserting heat dissipation layers into the vertical stack, between IC modules, or by placing a heat-dissipating sleeve around the stack. The IC modules themselves and/or heat-generating regions therein may be misaligned on their respective socket layers to further facilitate dissipating heat. Module stacks are scalable in that a user may add memory and/or processor modules as desired to increase device capability.

Abstract translation: 公开了用于在母板上垂直堆叠集成电路（IC）模块以节省主板空间并降低功耗的系统和方法。 IC模块可以包括处理器电路，存储器元件，通信电路等。每个IC模块上的引脚可以直接插入到下IC模块或耦合IC模块的插座层中。 通过将散热层插入垂直堆叠，IC模块之间，或者通过在堆叠周围放置散热套筒，可以消散由IC模块产生的热量。 IC模块本身和/或其中的发热区域可能在其相应的插座层上不对准，以进一步促进散热。 模块堆栈是可扩展的，因为用户可以根据需要添加内存和/或处理器模块以增加设备能力。

公开(公告)号：US20080284043A1

公开(公告)日：2008-11-20

申请号：US10598483

申请日：2005-02-23

Applicant: Robert-Christian Hagen ,  Jens Pohl

Inventor： Robert-Christian Hagen ,  Jens Pohl

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L23/4985 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/141 ,  H05K1/147 ,  H05K2201/049 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A base semiconductor component for a semiconductor component stack is disclosed. In one embodiment, the base semiconductor component has a semiconductor chip arranged centrally on a stiff wiring substrate. The wiring substrate has, in its edge regions, contact pads which are electrically connected to external contacts and at the same time to contact areas of the semiconductor chip and also to stack contact areas. The stack contact areas simultaneously form the upper side of the base semiconductor component and have an arrangement pattern corresponding to an arrangement pattern of external contacts of a semiconductor component to be stacked.

Abstract translation: 公开了一种用于半导体部件堆叠的基底半导体部件。 在一个实施例中，基底半导体部件具有中央布置在刚性布线基板上的半导体芯片。 布线基板在其边缘区域中具有电连接到外部触点并且同时接触半导体芯片的区域并且还与堆叠接触区域的接触焊盘。 堆叠接触区域同时形成基底半导体部件的上侧，并且具有对应于待堆叠的半导体部件的外部触头的布置图案的布置图案。

公开(公告)号：US20080244902A1

公开(公告)日：2008-10-09

申请号：US11783306

申请日：2007-04-09

Applicant: Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

Inventor： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

IPC: H05K3/00

CPC classification number: H05K1/186 ,  H01L23/4985 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/4611 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/10515 ,  H05K2201/10681 ,  Y10T29/49126 ,  Y10T29/49151 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/0401

Abstract: A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.

Abstract translation: 电路化衬底组件由至少两个电路化衬底组成，每个衬底均包括薄介电层和具有多个导电构件作为其一部分的导电层，每个衬底的导电构件电耦合到半导体芯片的导电部位。 电介质层位于两个基板之间，并且基板接合在一起，使得芯片在内部位于组件内并且以堆叠取向定向。 还提供了制造这种组件的方法，以及使用其的电组件以及适于将这种电组件作为其一部分的信息处理系统。

公开(公告)号：US07432131B2

公开(公告)日：2008-10-07

申请号：US11517366

申请日：2006-09-08

Applicant: Nobuaki Ebihara ,  Naoshi Suzuki

Inventor： Nobuaki Ebihara ,  Naoshi Suzuki

IPC: H01L29/74

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/144 ,  H05K1/145 ,  H05K3/321 ,  H05K3/3421 ,  H05K2201/0397 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10969 ,  H01L2924/00

Abstract: To mount a TSOP on an interposer substrate, leads provided to the TSOP are joined to pads of the interposer substrate by a thermosetting conductive resin, and the TSOP exclusive of the leads is joined to ground layers formed in the interposer substrate by a thermosetting conductive resin. The interposer substrates with the TSOPs mounted thereon are stacked in eight layers in such a manner that the TSOPs face downward. Then, leads of the upper interposer substrate are joined to pads formed in the rear face of the lower interposer substrate by a thermosetting conductive resin, so that the interposer substrates adjacent in a vertical direction are connected.

Abstract translation: 为了将TSOP安装在插入物基板上，通过热固性导电树脂将提供给TSOP的引线接合到插入器基板的焊盘，并且引线之外的TSOP通过热固性导电树脂与形成在插入器基板中的接地层接合 。 将其上安装有TSOP的插入物基板以使得TSOP面向下的方式以8层层叠。 然后，通过热固性导电树脂将上部插入器基板的引线接合到形成在下部插入器基板的后表面中的焊盘，使得在垂直方向上相邻的插入器基板被连接。

公开(公告)号：US20080198561A1

公开(公告)日：2008-08-21

申请号：US11943368

申请日：2007-11-20

Applicant: Koji OIWA

Inventor： Koji OIWA

IPC: H05K1/18

CPC classification number: H05K1/141 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0237 ,  H05K1/182 ,  H05K2201/09036 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: A high-frequency signal processing module has: a module base having a recess and a first connection terminal connectable to an external circuit board arranged on the open side of the recess; and a high-frequency signal processing circuit processing a high-frequency signal. The high-frequency signal processing circuit has a second connection terminal connectable to the external circuit board arranged on the open side of the recess of the module base, and is housed inside the recess of the module base. In this high-frequency signal processing module, the signal path along which a high-frequency signal fed through the external circuit board is received by the high-frequency signal processing circuit is short, contributing to a reduced parasitic inductive component.

Abstract translation: 高频信号处理模块具有：具有凹部的模块基座和可连接到设置在凹部的开放侧的外部电路板的第一连接端子; 以及处理高频信号的高频信号处理电路。 高频信号处理电路具有可连接到布置在模块基座的凹部的开放侧的外部电路板的第二连接端子，并且容纳在模块基座的凹部内。 在该高频信号处理模块中，通过高频信号处理电路接收通过外部电路板馈送的高频信号的信号路径很短，有助于降低寄生电感分量。

公开(公告)号：US20080192443A1

公开(公告)日：2008-08-14

申请号：US11852888

申请日：2007-09-10

Applicant: Hidefumi HATANAKA ,  Tsutomu ADACHI ,  Youichi YOKOTE ,  Miho IMASHIOYA ,  Tomohiko TANIGUCHI

Inventor： Hidefumi HATANAKA ,  Tsutomu ADACHI ,  Youichi YOKOTE ,  Miho IMASHIOYA ,  Tomohiko TANIGUCHI

IPC: H05K7/00 ,  H05K3/30

CPC classification number: H05K1/183 ,  H01L23/552 ,  H01L24/49 ,  H01L24/97 ,  H01L25/105 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/49109 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K3/0052 ,  H05K3/284 ,  H05K3/4611 ,  H05K3/4697 ,  H05K2201/09845 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/10689 ,  Y10T29/49133 ,  H01L2224/81 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An electronic component module comprises a circuit board having a cavity in one principal surface thereof. The electronic component module also comprises a first semiconductor device accommodated within the cavity and a second semiconductor device disposed on the one principal surface of the circuit board so as to cover the first semiconductor device in plan view. The electronic component module further comprises a resin material disposed to cover at least a side surface of the second semiconductor device.

Abstract translation: 电子部件模块包括其一个主表面中具有空腔的电路板。 电子部件模块还包括容纳在腔内的第一半导体器件和设置在电路板的一个主表面上的第二半导体器件，以便在平面图中覆盖第一半导体器件。 电子部件模块还包括设置成覆盖第二半导体器件的至少侧面的树脂材料。

公开(公告)号：US20080169543A1

公开(公告)日：2008-07-17

申请号：US11623075

申请日：2007-01-13

Applicant: Cheng-Lien Chiang

Inventor： Cheng-Lien Chiang

IPC: H01L23/02

CPC classification number: H01L25/105 ,  H01L25/18 ,  H01L2225/1005 ,  H01L2924/0002 ,  H05K1/181 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: A two dimensional stacking structure for integrated chip stacking on a printed circuit board having a controller electrically coupling on the printed circuit board, comprising a first integrated circuit package, a second integrated circuit package and two interposers. The first integrated circuit package is located beside the controller and electrically coupled on the printed circuit board, and has first leads. The second integrated circuit package is located on the controller, and has second leads. The two interposers having first metal contacts attaching to the corresponding first leads, second metal contacts attaching to the corresponding second leads, and circuit traces extending from the first metal contacts to the corresponding second metal contacts providing electrical communication between the first integrated circuit package and the second integrated package. The two dimensional stacking structure may be applied to a circuit module to decrease the profile of the circuit module.

Abstract translation: 一种用于在印刷电路板上集成芯片堆叠的二维堆叠结构，其具有电连接在印刷电路板上的控制器，包括第一集成电路封装，第二集成电路封装和两个插入件。 第一个集成电路封装位于控制器旁边，并电连接在印刷电路板上，并具有第一引线。 第二个集成电路封装位于控制器上，并具有第二个引线。 所述两个插入件具有附接到相应的第一引线的第一金属触点，附接到对应的第二引线的第二金属触点和从第一金属触点延伸到相应的第二金属触点的电路迹线，从而提供第一集成电路封装和 第二个集成包。 二维堆叠结构可以应用于电路模块以减小电路模块的轮廓。