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公开(公告)号：US20180316374A1
公开(公告)日：2018-11-01
申请号：US16029432
申请日：2018-07-06
Applicant: QUALCOMM Incorporated
Inventor： Changhan Yun , Chengjie Zuo , Mario Velez , Niranjan Sunil Mudakatte , Shiqun Gu , Jonghae Kim , David Berdy
IPC: H04B1/16 , H01L49/02 , H01L23/522 , H01L23/00 , H01L27/01 , H01L23/498 , H01L23/66 , H01L21/48 , H04B1/00
CPC classification number: H04B1/1638 , H01F17/0013 , H01L21/4853 , H01L21/486 , H01L23/49827 , H01L23/49838 , H01L23/5223 , H01L23/64 , H01L23/66 , H01L24/19 , H01L24/20 , H01L27/01 , H01L28/10 , H01L28/40 , H01L2223/6616 , H01L2223/6672 , H01L2223/6677 , H01L2223/6688 , H01L2224/04105 , H01L2224/24195 , H01L2924/10253 , H01L2924/13091 , H01L2924/1421 , H01L2924/15153 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H04B1/006 , H05K1/165 , H05K1/185 , H05K3/4605 , H05K2201/09536 , H05K2201/0959 , H05K2201/097 , H05K2201/09827
Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.
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公开(公告)号：US09980383B2
公开(公告)日：2018-05-22
申请号：US14748623
申请日：2015-06-24
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kuniaki Yosui , Masahiro Ozawa
IPC: H01H47/00 , H05K1/16 , H01L23/498 , H01G4/40 , H01G2/06 , H05K3/46 , H05K1/03 , H05K1/11 , H01F17/00 , H05K3/38
CPC classification number: H05K1/162 , H01F17/0006 , H01G2/06 , H01G4/40 , H01L23/49822 , H01L2224/16225 , H01L2924/19105 , H05K1/0313 , H05K1/111 , H05K1/115 , H05K1/165 , H05K3/383 , H05K3/4617 , H05K3/4632 , H05K2201/0129 , H05K2201/0355 , H05K2201/09527 , H05K2201/096 , H05K2201/09672 , H05K2201/097 , H05K2203/0278 , H05K2203/0307
Abstract: Sheets are laminated on each other and pressure bonded with fixtures from upper and lower directions of a lamination direction while being heated to produce a laminated circuit substrate including therein a capacitor and a coil. The capacitor is defined by a first conductor pattern and a second conductor pattern that face each other across thermoplastic resin layers. In the laminated circuit substrate, the first conductor pattern includes a first principal surface, the second conductor pattern includes a second principal surface, the first principal surface faces the second conductor pattern, the second principal surface faces the first conductor pattern, and the first principal surface and the second principal surface are subject to a roughening process.
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公开(公告)号：US20180065538A1
公开(公告)日：2018-03-08
申请号：US15808542
申请日：2017-11-09
Applicant: UUSI, LLC
Inventor： David W. Shank
CPC classification number: B60Q1/0088 , H01R12/62 , H05B33/0803 , H05B33/0845 , H05B33/0854 , H05B33/086 , H05B37/0227 , H05K1/02 , H05K1/117 , H05K1/14 , H05K1/142 , H05K1/16 , H05K2201/04 , H05K2201/09027 , H05K2201/09045 , H05K2201/09081 , H05K2201/09154 , H05K2201/09163 , H05K2201/097 , H05K2201/09709 , H05K2201/0979 , H05K2201/0999 , H05K2201/10053 , H05K2201/10151 , H05K2201/10356
Abstract: A vehicle accessory control component includes a first circuit board substrate and a second circuit board substrate. The first circuit board substrate has a plurality of circuit elements and an overall perimeter shape including an outer edge profile and a plurality of first deviations along the outer edge profile. The second circuit board substrate has a plurality of circuit elements an outer edge profile and a plurality of second deviations along the outer edge profile, at least one of the second deviations being different than the first deviations. The first circuit board substrate and the second circuit board substrate are arranged in a plane and selectively movable relative to each other to form the overall perimeter shape of the substrate. The outer edge profile of the first and second circuit board substrates are received in a housing having a correspondingly shaped perimeter that generally conforms to the outer edge profile.
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公开(公告)号：US20180049312A1
公开(公告)日：2018-02-15
申请号：US15792953
申请日：2017-10-25
Applicant: Amphenol Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, JR. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
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公开(公告)号：US09847565B2
公开(公告)日：2017-12-19
申请号：US14930937
申请日：2015-11-03
Applicant: RF Micro Devices, Inc.
Inventor： Dirk Robert Walter Leipold , George Maxim , Marcus Granger-Jones , Baker Scott
CPC classification number: H01P1/20381 , H01P5/028 , H01P9/006 , H05K1/00 , H05K1/0219 , H05K1/0239 , H05K1/0298 , H05K3/4611 , H05K2201/097
Abstract: The present disclosure relates to a tunable slow-wave transmission line. The tunable slow-wave transmission line is formed in a multi-layer substrate and includes an undulating signal path. The undulating signal path includes at least two loop structures, wherein each loop structure includes at least two via structures connected by at least one intra-loop trace. The undulating signal path further includes at least one inter-loop trace connecting the at least two loop structures. The tunable slow-wave transmission line includes a first ground structure disposed along the undulating signal path. Further, the tunable slow-wave transmission line includes one or more circuits that may alter a signal transmitted in the tunable slow-wave transmission line so as to tune a frequency of the signal.
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Patent Agency Ranking
公开(公告)号：US09840185B2
公开(公告)日：2017-12-12
申请号：US15362703
申请日：2016-11-28
Applicant: UUSI, LLC
Inventor： David W. Shank
CPC classification number: B60Q1/0088 , H01R12/62 , H05B33/0803 , H05B33/0845 , H05B33/0854 , H05B33/086 , H05B37/0227 , H05K1/02 , H05K1/117 , H05K1/14 , H05K1/142 , H05K1/16 , H05K2201/04 , H05K2201/09027 , H05K2201/09045 , H05K2201/09081 , H05K2201/09154 , H05K2201/09163 , H05K2201/097 , H05K2201/09709 , H05K2201/0979 , H05K2201/0999 , H05K2201/10053 , H05K2201/10151 , H05K2201/10356
Abstract: An illustrative inventory of vehicle accessory control components includes a plurality of first circuit boards and a plurality of second circuit boards. The first circuit boards each have a substrate with a plurality of circuit elements supported on the substrate. The first circuit board substrates have an overall perimeter shape including an outer edge profile and a plurality of first deviations from the outer edge profile. The second circuit boards each have a substrate with a plurality of circuit elements supported on them. The second circuit board substrates have the overall perimeter shape including the same outer edge profile as the first circuit board substrates. The second circuit board substrates include a plurality of second deviations from the outer edge profile. At least one portion of the second deviations is different than the first deviations of the first circuit boards.
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公开(公告)号：US09807869B2
公开(公告)日：2017-10-31
申请号：US14947166
申请日：2015-11-20
Applicant: Amphenol Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, Jr. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
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158.发明申请公开(公告)号：US20170133775A1
公开(公告)日：2017-05-11
申请号：US15409689
申请日：2017-01-19
Applicant: Lear Corporation
Inventor： Bert W. Eakins , George E. Fox
CPC classification number: H01R12/707 , H01R4/02 , H01R4/028 , H01R12/585 , H01R43/205 , H05K3/3447 , H05K3/4015 , H05K2201/097 , H05K2201/10295 , H05K2201/10787 , H05K2201/10871 , H05K2201/2072 , H05K2203/047 , H05K2203/1572
Abstract: A circuit board assembly may include a circuit board, a first electrical terminal, and a layer of solder paste. The circuit board may include a minimum thickness, a first side, and a second side opposite the first side. The first electrical terminal may include a solder tab. The layer of solder paste may be disposed on the first side of the circuit board. The solder tab of the first electrical terminal may extend into the first side of the circuit board but not beyond the second side of the circuit board.
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公开(公告)号：US20170084976A1
公开(公告)日：2017-03-23
申请号：US15364899
申请日：2016-11-30
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Nobuo IKEMOTO , Yuki WAKABAYASHI , Shigeru TAGO
CPC classification number: H01P3/082 , H01P3/08 , H01P11/003 , H01R12/62 , H01R24/50 , H01R2103/00 , H05K1/0219 , H05K1/0225 , H05K1/024 , H05K1/0242 , H05K1/0253 , H05K1/115 , H05K1/118 , H05K1/147 , H05K3/0052 , H05K3/363 , H05K3/4623 , H05K3/4632 , H05K2201/07 , H05K2201/09154 , H05K2201/0919 , H05K2201/09481 , H05K2201/09527 , H05K2201/096 , H05K2201/09618 , H05K2201/097 , H05K2201/09845 , H05K2201/10037 , H05K2201/10204 , Y10T29/49016
Abstract: In a high frequency signal line, a first signal line extends along a first dielectric element assembly, a first reference ground conductor extends along the first signal line, a second signal line is provided in or on the second dielectric element assembly and extends along the second dielectric element assembly, a second reference ground conductor is provided in or on the second dielectric element assembly and extends along the second signal line. A portion of a bottom surface at an end of the first dielectric element assembly and a portion of the top surface at an end of the second dielectric element assembly are joined together such that a joint portion of the first and second dielectric element assemblies includes a corner. The second signal line and the first signal line are electrically coupled together. The first and second reference ground conductors are electrically coupled together.
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公开(公告)号：US09583809B2
公开(公告)日：2017-02-28
申请号：US14509285
申请日：2014-10-08
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Noboru Kato , Satoshi Ishino , Jun Sasaki
CPC classification number: H01P3/003 , H01P3/026 , H01P3/08 , H01P3/082 , H01P3/085 , H01P5/028 , H05K1/0225 , H05K1/0251 , H05K2201/09245 , H05K2201/09336 , H05K2201/09636 , H05K2201/097
Abstract: A high-frequency signal line includes a body with a first layer level and a second layer level; a signal line including a first line portion provided at the first layer level, a second line portion provided at the second layer level, and a first interlayer connection connecting the first line portion and the second line portion; a first ground conductor including a first ground portion provided at the first layer level; a second ground conductor including a second ground portion provided at the second layer level; and a second interlayer connection connecting the first ground portion and the second ground portion. A distance between the first interlayer connection and the second interlayer connection is not less than a maximum distance between the first line portion and the first ground portion and is not less than a maximum distance between the second line portion and the second ground portion.
Abstract translation: 高频信号线包括具有第一层级和第二层级的主体; 信号线，包括设置在第一层级的第一线部分，设置在第二层级的第二线部分和连接第一线部分和第二线部分的第一层间连接; 第一接地导体，包括设置在第一层级的第一接地部分; 第二接地导体，包括设置在第二层级的第二接地部分; 以及连接所述第一接地部和所述第二接地部的第二层间连接。 第一层间连接和第二层间连接之间的距离不小于第一线部分和第一接地部分之间的最大距离，并且不小于第二线路部分和第二接地部分之间的最大距离。
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