公开(公告)号：US20020023895A1

公开(公告)日：2002-02-28

申请号：US09789771

申请日：2001-02-22

Applicant: FUJITSU LIMITED

Inventor： Kenji Iida

IPC: H01B013/00

CPC classification number: H05K3/108 ,  H05K3/045 ,  H05K3/243 ,  H05K3/4647 ,  H05K2201/09881 ,  H05K2203/025 ,  H05K2203/054 ,  H05K2203/0542 ,  H05K2203/0733 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: In the multilayer circuit board, cable patterns in a plurality of cable layers can be precisely formed, and the cable layer are formed with higher density, with higher reliability. The multilayer circuit board comprises: a plurality of cable layers, each of which includes electric conductive sections; a plurality of first insulating layers, each of which encloses the electric conductive sections in each cable layer and fills spaces between the electric conductive sections; and post vias electrically connecting the electric conductive sections in one cable layer to those in another cable layer. Height of the electric conductive sections in each cable layer are equal to that of the first insulating layer enclosing those electric conductive sections.

Abstract translation: 在多层电路板中，可以精确地形成多个电缆层中的电缆图案，并且以更高的可靠性形成更高密度的电缆层。 多层电路板包括：多个电缆层，每个电缆层包括导电部分; 多个第一绝缘层，每个绝缘层包围每个电缆层中的导电部分，并且填充导电部分之间的空间; 以及将一个电缆层中的导电部分电连接到另一电缆层中的导电部分的通孔。 每个电缆层中的导电部分的高度等于封装这些导电部分的第一绝缘层的高度。

公开(公告)号：US06323435B1

公开(公告)日：2001-11-27

申请号：US09363959

申请日：1999-07-29

Applicant: Jan I. Strandberg ,  David J. Chazan ,  Michael P. Skinner

Inventor： Jan I. Strandberg ,  David J. Chazan ,  Michael P. Skinner

IPC: H05K103

CPC classification number: H05K1/0271 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4673 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2203/0353 ,  H05K2203/0585 ,  H05K2203/0759 ,  H05K2203/1476 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2224/05647

Abstract: Low-impedance high density deposited-on-laminate (DONL) structures having reduced stress features reducing metallization present on the laminate printed circuit board. In this manner, reduced is the force per unit area exerted on the dielectric material disposed adjacent to the laminate material that is typically present during thermal cycling of the structure.

Abstract translation: 具有降低的应力特征的低阻抗高密度叠层（DONL）结构减少层压印刷电路板上存在的金属化。 以这种方式，减小了施加在邻近层压材料设置的电介质材料上的每单位面积的力，其通常在结构的热循环过程中存在。

公开(公告)号：US20010037898A1

公开(公告)日：2001-11-08

申请号：US09815234

申请日：2001-03-22

Inventor： Bharat Z. Patel ,  Jay D. Baker ,  Mohan R. Paruchuri

IPC: H05K001/11

CPC classification number: H05K3/462 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method 10, 90 for making a multi-layer electronic circuit board 82, 168 including the steps of forming at least one protuberance 15, 100 upon an electrically conductive member 12, 92 and adding additional electrically conductive layers of material 34, 56, 58, 104, 114, 138, 140 to the member 12, 92 while selectively extending the protuberance 15, 100 within the layers 82, 168, thereby forming a circuit board 82, 168. A portion of the formed circuit board may be etched in order to selectively create air-bridges 86 or interconnection portions 164.

Abstract translation: 一种用于制造多层电子电路板82,168的方法10,90，包括在导电构件12,92上形成至少一个突起15,100的步骤，并且添加另外的材料34,56,58的导电层 ，104,114,138,140连接到构件12,92，同时在层82,168内选择性地延伸突起15,100，从而形成电路板82,168。形成的电路板的一部分可以按顺序蚀刻 以选择性地产生空气桥86或互连部分164。

公开(公告)号：US06251502B1

公开(公告)日：2001-06-26

申请号：US09357659

申请日：1999-07-20

Applicant: Toshihiko Yasue ,  Yasuji Hiramatsu ,  Hideki Yano ,  Yoshifumi Ishitani ,  Yoichiro Kawamura ,  Hideki Murase ,  Ayumi Suzuki ,  Masato Kawade ,  Motoo Asai

Inventor： Toshihiko Yasue ,  Yasuji Hiramatsu ,  Hideki Yano ,  Yoshifumi Ishitani ,  Yoichiro Kawamura ,  Hideki Murase ,  Ayumi Suzuki ,  Masato Kawade ,  Motoo Asai

IPC: B32B300

CPC classification number: H05K3/4661 ,  H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773 ,  Y10S428/901 ,  Y10T428/24893 ,  Y10T428/24917 ,  Y10T428/252

Abstract: It is to provide a multilayer printed circuit board having excellent resolution, interlaminar insulation property and resistance to cool-heat shock without forming unevenness on the surface and lowering peel strength even if the thickness of the resin insulating layer is thin. The invention proposes a multilayer printed circuit board comprising an upper conductor circuit layer, a lower conductor circuit layer and a resin insulating layer electrically insulating both the conductor circuit layers, in which the resin insulating layer is a composite layer comprised of an layer made from a heat-resistant resin hardly soluble in acid or oxidizing agent as a lower layer and an adhesive layer for electroless plating made from a heat-resistant resin as an upper layer, and if necessary, a resin is filled in a concave portion created between conductor insulating circuits of the lower layer so as to render the surface into the same plane as the surface of the conductor circuit.

Abstract translation: 提供一种具有优异的分辨率，层间绝缘性和耐冷热冲击性的多层印刷电路板，而不会在表面上形成不均匀性，并且即使树脂绝缘层的厚度薄，也降低剥离强度。 本发明提出了一种多层印刷电路板，包括上导体电路层，下导体电路层和电绝缘两个导体电路层的树脂绝缘层，其中树脂绝缘层是由由 耐热树脂难溶于作为下层的酸或氧化剂以及由耐热树脂作为上层制成的用于化学镀的粘合剂层，如果需要，树脂填充在导体绝缘 电路，以使表面进入与导体电路的表面相同的平面。

公开(公告)号：US06217988B1

公开(公告)日：2001-04-17

申请号：US09432080

申请日：1999-11-02

Applicant: Toshihiko Yasue ,  Yasuji Hiramatsu ,  Hideki Yano ,  Yoshifumi Ishitani ,  Yoichiro Kawamura ,  Hideki Murase ,  Ayumi Suzuki ,  Masato Kawade ,  Motoo Asai

Inventor： Toshihiko Yasue ,  Yasuji Hiramatsu ,  Hideki Yano ,  Yoshifumi Ishitani ,  Yoichiro Kawamura ,  Hideki Murase ,  Ayumi Suzuki ,  Masato Kawade ,  Motoo Asai

IPC: B32B300

CPC classification number: H05K3/4661 ,  H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773 ,  Y10S428/901 ,  Y10T428/24893 ,  Y10T428/24917 ,  Y10T428/252

Abstract: It is to provide a multilayer printed circuit board having excellent resolution, interlaminar insulation property and resistance to cool-heat shock without forming unevenness on the surface and lowering peel strength even if the thickness of the resin insulating layer is thin. The invention proposes a multilayer printed circuit board comprising an upper conductor circuit layer, a lower conductor circuit layer and a resin insulating layer electrically insulating both the conductor circuit layers, in which the resin insulating layer is a composite layer comprised of an layer made from a heat-resistant resin hardly soluble in acid or oxidizing agent as a lower layer and an adhesive layer for electroless plating made from a heat-resistant resin as an upper layer, and if necessary, a resin is filled in a concave portion created between conductor insulating circuits of the lower layer so as to render the surface into the same plane as the surface of the conductor circuit.

公开(公告)号：US6037096A

公开(公告)日：2000-03-14

申请号：US85117

申请日：1998-05-26

Applicant: Mary Beth Fletcher ,  Robert L. Nedbalski ,  Konstantinos I. Papathomas ,  Amarjit Singh Rai

Inventor： Mary Beth Fletcher ,  Robert L. Nedbalski ,  Konstantinos I. Papathomas ,  Amarjit Singh Rai

IPC: H05K3/00 ,  H05K3/28 ,  G03C11/12 ,  B32B3/00

CPC classification number: H05K3/0094 ,  H05K3/28 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0278 ,  Y10T428/24802

Abstract: The present invention relates to a method for planarizing circuit board apertures wherein a photoimageable film composition comprising a photoimageable dielectric composition and a support film is employed to fill the circuit board apertures. Precircuitized and postcircuitized embodiments are discussed.

Abstract translation: 本发明涉及一种用于平面化电路板孔径的方法，其中采用包含可光成像的电介质组合物和支撑膜的可光成象的膜组合物来填充电路板孔。 讨论了前电路和后电路的实施例。

公开(公告)号：US5987744A

公开(公告)日：1999-11-23

申请号：US888348

申请日：1997-07-01

Applicant: James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  John Y. Xie

Inventor： James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  John Y. Xie

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/06 ,  H05K3/20 ,  H05K3/40 ,  H05K3/44 ,  H01K3/10

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K3/445 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/09881 ,  H05K2203/0323 ,  H05K2203/0733 ,  H05K3/06 ,  H05K3/205 ,  H05K3/4069 ,  Y10T29/49165

Abstract: A structure includes a support layer formed of a conductive material, such as a sheet of copper. The support layer has a number of conductive islands isolated from other portions of the support layer by isolation gaps. The support layer is sandwiched between two compound layers each of which is formed of a dielectric layer having a number of via holes and conductive elements located in the via holes. The conductive elements are formed at predetermined locations such that a conductive element in each compound layer contacts a conductive island in the support layer. The structure also includes two conductive layers formed on the two respective compound layers such that a trace in a first conductive layer is coupled to a trace in a second conductive layer through two conductive elements in the respective two compound layers and an island in the support layer. Such a structure can be formed by a number of processes. For example, the support layer can be formed by etching a sheet of conductive material, the compound layers can be formed by placing a conductive paste in via holes in a dielectric layer, and the conductive layers can be formed by lamination followed by etching to form traces.

Abstract translation: 结构包括由诸如铜片的导电材料形成的支撑层。 支撑层具有通过隔离间隙与支撑层的其它部分隔离的多个导电岛。 支撑层夹在两个化合物层之间，每个化合物层由具有多个通孔的电介质层和位于通孔中的导电元件形成。 导电元件形成在预定位置，使得每个化合物层中的导电元件接触支撑层中的导电岛。 该结构还包括在两个相应化合物层上形成的两个导电层，使得第一导电层中的迹线通过两个化合物层中的两个导电元件和支撑层中的岛耦合到第二导电层中的迹线 。 这样的结构可以通过多个过程形成。 例如，可以通过蚀刻导电材料片形成支撑层，可以通过在电介质层中的通孔中放置导电膏来形成化合物层，并且可以通过层压形成导电层，然后进行蚀刻以形成 痕迹

公开(公告)号：US5916407A

公开(公告)日：1999-06-29

申请号：US727671

申请日：1995-06-27

Applicant: Werner Gruenwald ,  Ralf Haug ,  Thomas Burkhart ,  Martin Mennig ,  Helmut Schmidt

Inventor： Werner Gruenwald ,  Ralf Haug ,  Thomas Burkhart ,  Martin Mennig ,  Helmut Schmidt

IPC: H01R4/04 ,  H05K1/18 ,  H05K3/32 ,  H05K3/36 ,  H05K13/04

CPC classification number: H01R4/04 ,  H05K3/321 ,  H05K3/361 ,  H05K1/181 ,  H05K2201/0129 ,  H05K2201/09881 ,  H05K2201/10674 ,  H05K2201/10984 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/0534 ,  H05K2203/1173 ,  H05K3/1275 ,  Y10T29/53174

Abstract: A process for producing an electrically conductive connection between opposite arranged contact areas of two elements that are to be connected, by means of a hot-melt type adhesive formed of electrically conductive particles, which are dispersed in a thermoplastic base material. The hot-melt type adhesive (22) is applied purposely only to the contact areas (16) of at least one of the elements (10, 28, 42, 50) and that these elements are joined under the effects of heat.

Abstract translation: PCT No.PCT / DE95 / 00830 Sec。 371日期1996年10月17日第 102（e）日期1996年10月17日PCT提交1995年6月27日PCT公布。 出版物WO96 / 02955 日期：1996年2月1日，一种用于通过由导电颗粒形成的热熔型粘合剂将待连接的两个元件的相对布置的接触区域之间的导电连接制造的方法，该粘合剂分散在热塑性基材 。 热熔型粘合剂（22）仅专门应用于至少一个元件（10,28,42,50）的接触区域（16），并且这些元件在热作用下接合。

公开(公告)号：US5760502A

公开(公告)日：1998-06-02

申请号：US691774

申请日：1996-08-02

Applicant: Evert J. Van Loenen ,  Gerardus N. A. Van Veen

Inventor： Evert J. Van Loenen ,  Gerardus N. A. Van Veen

IPC: H01F41/04 ,  H02K3/26 ,  H02K3/50 ,  H02K15/04 ,  H05K1/02 ,  H05K1/16 ,  H05K3/00 ,  H05K3/10 ,  H05K3/24 ,  H02K3/04 ,  H02K3/32

CPC classification number: H05K1/0265 ,  H02K3/26 ,  H05K3/24 ,  H05K1/165 ,  H05K2201/0347 ,  H05K2201/098 ,  H05K2201/09881 ,  Y10S310/06 ,  Y10T29/49155

Abstract: A method of manufacturing a pattern of conductors on a polyimide base is disclosed. After the conductors have been formed in known manner, ridges of an insulating material are formed in the metal free zones by applying, exposing and developing a UV-sensitive resist. Subsequently, metal is deposited on the conductors between the ridges, which prevent short circuits.

Abstract translation: 公开了一种在聚酰亚胺基底上制造导体图案的方法。 在以已知的方式形成导体之后，通过施加，曝光和显影UV敏感抗蚀剂，在无金属区域中形成绝缘材料的脊。 随后，金属沉积在脊之间的导体上，防止短路。

公开(公告)号：US5541567A

公开(公告)日：1996-07-30

申请号：US323554

申请日：1994-10-17

Applicant: Keith E. Fogel ,  Jeffrey C. Hedrick ,  David A. Lewis ,  Eva E. Simonyi ,  Alfred Viehbeck ,  Stanley J. Whitehair

Inventor： Keith E. Fogel ,  Jeffrey C. Hedrick ,  David A. Lewis ,  Eva E. Simonyi ,  Alfred Viehbeck ,  Stanley J. Whitehair

IPC: H01F17/00 ,  H05K1/05 ,  H05K3/40 ,  H05K3/44 ,  H01F5/00 ,  H05K1/16

CPC classification number: H05K3/445 ,  H01F17/0006 ,  H05K1/056 ,  H05K2201/09636 ,  H05K2201/09881 ,  H05K2201/10416 ,  H05K3/4046

Abstract: Structures are described having vias with more than one electrical conductor at least one of which is a solid conductor which is formed by inserting the wire into the via in a substrate wherein the wire is attached to an electrically conductive plate which is spaced apart from the substrate by a spacer which leave a space between the substrate and plate. The space is filled with a dielectric material. The space with via between the conductor and via sidewall is filled with a dielectric material. The via is used for making transformers and inductors wherein one of the via conductors is used for inner windings and another of the via conductors is used for outer windings.

Abstract translation: 描述了具有多于一个电导体的通孔的结构，其中至少一个电导体是通过将电线插入基板中的通孔而形成的实心导体，其中导线附接到与基板间隔开的导电板 通过在基板和板之间留下空隙的间隔件。 该空间填充有电介质材料。 在导体和通孔侧壁之间具有通孔的空间填充有电介质材料。 通孔用于制造变压器和电感器，其中通孔导体之一用于内部绕组，另一个通孔导体用于外部绕组。