公开(公告)号：US09185808B2

公开(公告)日：2015-11-10

申请号：US13715947

申请日：2012-12-14

Applicant: PEKING UNIVERSITY FOUNDER GROUP CO., LTD. ,  ZHUHAI FOUNDER TECH. HI-DENSITY ELECTRONIC CO., LTD. ,  ZHUHAI FOUNDER PCB DEVELOPMENT CO., LTD.

Inventor： Lanyuan Chen ,  Haode Li

IPC: G06F17/50 ,  H05K3/00 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K3/0005 ,  H05K1/0296 ,  H05K1/111 ,  H05K2201/09381 ,  H05K2201/10734 ,  Y02P70/611

Abstract: The invention discloses a printed circuit board compensation processing method for fabricating a BGA despite a small distance between a line and a pad of the BGA. The method includes compensating a pad and/or a line under a predetermined condition, and removing a portion of the pad facing the line by a second predetermined width when the shortest distance between the compensated line and pad is smaller than a first predetermined distance. The invention further discloses a device for performing the method and a PCB fabricated using the method.

Abstract translation: 本发明公开了一种用于制造BGA的印刷电路板补偿处理方法，尽管BGA的线和焊盘之间的距离很小。 所述方法包括在预定条件下补偿焊盘和/或线，以及当所述经补偿的线和焊盘之间的最短距离小于第一预定距离时，将面向所述线的所述焊盘的一部分移除第二预定宽度。 本发明还公开了一种用于执行该方法的装置和使用该方法制造的PCB。

公开(公告)号：US20150282316A1

公开(公告)日：2015-10-01

申请号：US14543303

申请日：2014-11-17

Applicant: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD. ,  HON HAI PRECISION INDUSTRY CO., LTD.

Inventor： ZHANG-LONG PENG ,  CHUN-SHENG CHEN

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/09

CPC classification number: H05K1/111 ,  H05K1/09 ,  H05K1/181 ,  H05K3/3421 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/10242 ,  H05K2201/10992 ,  Y02P70/611

Abstract: A printed circuit board which avoids the melding of closely adjacent solders includes a top surface, a number of electronic elements and a number of solders. The top surface includes a plurality of copper clad areas. Each copper clad area includes a head area and a neck area. The neck area is positioned on same side of the head area. The neck area includes two edges extended from a fringe of the head area and a terminal point. The two edges intersect at the terminal point. The electronic elements are positioned at the head area. Each solder includes a soldering portion and a tip portion. The soldering portion is attached on the head area and surrounds the electronic element. The tip portion is attached on the neck area. A fringe of the solder is same as the fringe of the copper clad area.

Abstract translation: 避免紧密相邻的焊料熔接的印刷电路板包括顶表面，多个电子元件和多个焊料。 顶表面包括多个铜包覆区域。 每个铜包覆区域包括头部区域和颈部区域。 颈部区域位于头部区域的同一侧。 颈部区域包括从头部区域的边缘延伸的两个边缘和终点。 两个边缘在终点处相交。 电子元件位于头部区域。 每个焊料包括焊接部分和尖端部分。 焊接部分附着在头部区域上并围绕电子元件。 尖端部分附着在颈部区域。 焊料的边缘与铜包覆区域的边缘相同。

公开(公告)号：US20150245483A1

公开(公告)日：2015-08-27

申请号：US14632574

申请日：2015-02-26

Applicant: NISSIN KOGYO CO., LTD.

Inventor： Sakae MIYASAKA

IPC: H05K1/11 ,  B60T15/02

CPC classification number: B60T15/028 ,  H05K3/325 ,  H05K3/4015 ,  H05K2201/09154 ,  H05K2201/09381 ,  H05K2201/10151 ,  H05K2203/048

Abstract: One embodiment provides a circuit board having a substrate and an electrode portion which is provided on the substrate. The electrode portion includes: a quadrangular land which is provided on a front surface of the substrate; a solder layer which is laminated on the whole of a front surface of the land; and a pad which is joined to a front surface of the solder layer. When the electrode portion is seen from thereabove, an outer circumferential line of the pad touches each of four sides of the land. Exposed portions where the solder layer is exposed are formed individually at four corners of a front surface of the electrode portion. And, the exposed portions are formed to have the same shape.

Abstract translation: 一个实施例提供一种具有基板和设置在基板上的电极部分的电路板。 电极部分包括：设置在基板的前表面上的四边形区域; 层叠在所述焊盘的前表面的整体上的焊料层; 以及与焊料层的前表面接合的焊盘。 当从上方观察电极部分时，焊盘的外周线接触焊盘的四边中的每一侧。 焊料层露出的露出部分分别形成在电极部分的前表面的四个角处。 并且，露出部分形成为具有相同的形状。

公开(公告)号：US20150136467A1

公开(公告)日：2015-05-21

申请号：US14408039

申请日：2013-03-13

Applicant: HSIO TECHNOLOGIES, LLC

Inventor： James Rathburn

IPC: H01R12/77 ,  H01R12/82 ,  H01R12/79

CPC classification number: H01R23/6813 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01R12/73 ,  H01R12/82 ,  H01R13/2457 ,  H01R13/2485 ,  H01R31/06 ,  H05K1/092 ,  H05K1/111 ,  H05K1/141 ,  H05K1/182 ,  H05K3/0094 ,  H05K3/10 ,  H05K3/1291 ,  H05K3/326 ,  H05K3/363 ,  H05K3/365 ,  H05K3/4007 ,  H05K3/4015 ,  H05K3/4092 ,  H05K3/425 ,  H05K3/4694 ,  H05K7/1076 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/09381 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2201/10386 ,  H05K2201/2072 ,  H05K2201/209 ,  H05K2203/041 ,  H05K2203/1476 ,  Y10T29/49165 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.

Abstract translation: 一种在电路组件上制成集成端子阵列的方法。 该方法包括以下步骤：在第一电路构件的第一表面上沉积至少第一液体电介质层，成像为包括与集成端子阵列相对应的多个第一凹部。 处理第一凹槽的选定表面以接受无电导电电镀沉积。 对所述第一凹槽的所选择的表面施加无电镀以产生电耦合到所述第一电路层并且大致垂直于所述第一电路层延伸的多个第一导电结构。 使用导电材料将电镀施加到基本上第一凹部的无电镀。 重复沉积，加工，无电镀和电镀的步骤以形成所需形状的整体端子。 去除电介质层以露出端子。

公开(公告)号：US09006912B2

公开(公告)日：2015-04-14

申请号：US13544809

申请日：2012-07-09

Applicant: Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Ken Jian Ming Wang ,  Cheemen Yu ,  Hem Takiar

Inventor： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Ken Jian Ming Wang ,  Cheemen Yu ,  Hem Takiar

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K1/111 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/0195 ,  H05K2201/0338 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10159 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Abstract translation: 公开了具有共同的电连接器和接触焊盘区域的印刷电路板。 迹线和/或通孔所在接触焊盘区域可被蚀刻掉，以确保迹线，通孔和接触焊盘之间的电气隔离。

公开(公告)号：US20150068791A1

公开(公告)日：2015-03-12

申请号：US14484675

申请日：2014-09-12

Applicant: IBIDEN CO., LTD.

Inventor： Takenobu NAKAMURA

IPC: H05K1/11 ,  H05K3/00 ,  H05K1/18 ,  H05K3/10 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K1/111 ,  H05K1/113 ,  H05K3/3452 ,  H05K2201/09381 ,  Y02P70/611 ,  Y10T29/4916

Abstract: A wiring board includes a substrate, pads formed on an electronic-component mounting surface of the substrate, and a resin insulation layer covering the electronic-component mounting surface and having opening portions such that the opening portions are exposing the pads, respectively. The pads include a non-solder mask defined pad having a wiring portion and a non-solder mask defined pad having no wiring portion, and the opening portions are formed such that the non-solder mask defined pads have exposed conductor areas which have substantially same areas inside the opening portions.

Abstract translation: 布线基板包括基板，形成在基板的电子元件安装面上的焊盘以及覆盖电子部件安装面的树脂绝缘层，并且具有分别露出焊盘的开口部的开口部。 焊盘包括具有布线部分的非焊锡掩模限定的焊盘和不具有布线部分的非焊料掩模限定的焊盘，并且形成开口部分，使得非焊料掩模限定的焊盘具有暴露的具有基本相同的导体区域 开口部分内的区域。

公开(公告)号：US08890326B2

公开(公告)日：2014-11-18

申请号：US13559622

申请日：2012-07-27

Applicant: Kai-Wen Wu

Inventor： Kai-Wen Wu

IPC: H01L23/48

CPC classification number: H01L24/83 ,  H01L24/29 ,  H01L2224/26165 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83874 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15153 ,  H05K1/0274 ,  H05K3/305 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/2018 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A chip assembly includes a PCB, a connecting pad fixed on the PCB, and a chip. The connecting pad defines a through hole. The chip is received in the through hole and fixed on the PCB by an adhesive distributed in the through hole. A thickness of the adhesive is less than that of the connecting pad.

Abstract translation: 芯片组件包括PCB，固定在PCB上的连接焊盘和芯片。 连接垫定义一个通孔。 芯片被容纳在通孔中并通过分布在通孔中的粘合剂固定在PCB上。 粘合剂的厚度小于连接垫的厚度。

公开(公告)号：US20140312488A1

公开(公告)日：2014-10-23

申请号：US14230188

申请日：2014-03-31

Applicant: FUJITSU LIMITED

Inventor： Takashi FUKUDA

IPC: H01L23/00

CPC classification number: H01L23/3128 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0234 ,  H05K1/0286 ,  H05K1/0295 ,  H05K1/113 ,  H05K1/167 ,  H05K2201/045 ,  H05K2201/09381 ,  H05K2201/10159 ,  H05K2201/10378 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing a wiring board unit, the wiring board unit including a semiconductor package that includes a memory chip, a wiring board on which the semiconductor package is mounted, and an insertion base inserted between the wiring board and the semiconductor package, the method includes: forming a plurality of connection portion groups in a base material, the connection portion groups each including a plurality of connection portions that each electrically connect a board-side pad of the wiring board and an external terminal of the semiconductor package to each other; forming the insertion base such that resistances of the connection portions included in the connection portion groups are adjusted in accordance with types of target memory chips; and connecting the external terminals and the board-side pads to one another by using the connection portion group selected in accordance with the type of the memory chip.

Abstract translation: 一种制造布线基板单元的方法，所述布线基板单元包括半导体封装，其包括存储芯片，安装有所述半导体封装的布线基板和插入在所述布线板和所述半导体封装之间的插入基板，所述方法 包括：在基材中形成多个连接部分组，所述连接部分包括多个连接部分，每个连接部分将所述布线板的板侧焊盘和所述半导体封装的外部端子彼此电连接; 形成插入基座，使得包括在连接部分组中的连接部分的电阻根据目标存储芯片的类型进行调节; 以及通过使用根据存储芯片的类型选择的连接部分组将外部端子和电路板侧焊盘彼此连接。

公开(公告)号：US20140168909A1

公开(公告)日：2014-06-19

申请号：US13719506

申请日：2012-12-19

Applicant: Tieyu Zheng ,  Jin A. Zhao ,  Ru Han ,  Min Pei

Inventor： Tieyu Zheng ,  Jin A. Zhao ,  Ru Han ,  Min Pei

IPC: H05K1/18 ,  H05K1/03

CPC classification number: H05K3/3452 ,  H05K1/111 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/0969 ,  H05K2201/0989 ,  H05K2201/099 ,  Y02P70/611

Abstract: Attachment structures for electrically coupling a microelectronic package to a microelectronic board/interposer including joint pads formed on the microelectronic board/interposer which provide a gap between respective openings in a solder resist layer of the microelectronic substrate and each of the joint pads. Such attachment structures may reduce or substantially eliminate contact between a solder interconnect and a solder resist layer of the microelectronic board/interposer, which may, in turn, reduce or substantially eliminate the potential of crack initiation and propagation at contact areas between the solder interconnect and a solder resist layer of the microelectronic board/interposer due to stresses induced by a mismatch of thermal expansion between the microelectronic package and the microelectronic board/interposer during thermal cycling. Further, the connection area between the pad and outside circuitry may be maximized, so that the impact to electrical performance due to the pad design may be minimized.

Abstract translation: 用于将微电子封装电耦合到包括形成在微电子板/插入件上的接合焊盘的微电子板/插入件的附接结构，其提供微电子衬底的阻焊层中的各个开口之间的间隙以及每个接合焊盘。 这种附接结构可以减少或基本上消除微电子板/插入件的焊料互连和阻焊层之间的接触，这又可以减少或基本消除在焊料互连和焊接互连之间的接触区域处的裂纹发生和传播的可能性 由于在热循环期间微电子封装和微电子板/插入件之间的热膨胀不匹配引起的应力，微电子板/插入件的阻焊层。 此外，焊盘和外部电路之间的连接区域可以最大化，使得由于焊盘设计而对电性能的影响可能被最小化。

公开(公告)号：US08669665B2

公开(公告)日：2014-03-11

申请号：US12478128

申请日：2009-06-04

Applicant: Yasushi Araki ,  Seiji Sato ,  Masatoshi Nakamura ,  Takashi Ozawa

Inventor： Yasushi Araki ,  Seiji Sato ,  Masatoshi Nakamura ,  Takashi Ozawa

IPC: H01L23/498

CPC classification number: H05K3/3452 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/10175 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H05K2201/09381 ,  H05K2201/099 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A solder resist and a central pad to which a central Au bump provided on a semiconductor chip is flip-chip bonded are formed on a substrate main body. In a flip-chip mounting substrate where an underfill resin is provided after the semiconductor chip is mounted, a central opening portion for exposing the central pad is formed in the solder resist, and also, an edge portion forming the central opening portion of the solder resist is partially overlapped with the outer peripheral portion of the central pad.

Abstract translation: 在衬底主体上形成阻焊剂和设置在半导体芯片上的中心Au凸块倒装芯片接合的中心焊盘。 在安装半导体芯片之后设置底部填充树脂的倒装芯片安装基板中，在阻焊层中形成用于暴露中心焊盘的中心开口部分，并且还形成形成焊料的中心开口部分的边缘部分 抗蚀剂部分地与中心焊盘的外周部分重叠。