公开(公告)号：US07259336B2

公开(公告)日：2007-08-21

申请号：US10861387

申请日：2004-06-07

Applicant: Aneta Wyrzykowska ,  Herman Kwong ,  Luigi Difilippo

Inventor： Aneta Wyrzykowska ,  Herman Kwong ,  Luigi Difilippo

IPC: H01R12/04

CPC classification number: H05K1/112 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734

Abstract: A technique for improving power/ground flooding is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving power and ground flooding in a multilayer circuit board, the multilayer circuit board having a plurality of signal layers. The method may comprise forming a plurality of electrically conductive vias, wherein each of the plurality of electrically conductive vias extends through one or more of the plurality of signal layers. The method may also comprise routing signals associated with the plurality of electrically conductive vias, thereby creating at least one power/ground flooding channel. The method may additionally comprise forming at least one power/ground connection within the at least one power/ground flooding channel.

Abstract translation: 公开了一种改善电力/地面淹没的技术。 在一个特定的示例性实施例中，该技术可以被实现为用于改进多层电路板中的功率和地面淹没的方法，所述多层电路板具有多个信号层。 该方法可以包括形成多个导电通孔，其中多个导电通孔中的每一个延伸穿过多个信号层中的一个或多个。 该方法还可以包括与多个导电通孔相关联的路由信号，从而产生至少一个电力/地面淹没通道。 该方法可以另外包括在至少一个电力/地面淹没通道内形成至少一个电力/接地连接。

公开(公告)号：US20070181928A1

公开(公告)日：2007-08-09

申请号：US11508141

申请日：2006-08-23

Applicant: Yoshiki Yamanishi ,  Muneo Harada ,  Takahiro Kitano ,  Tatsuzo Kawaguchi ,  Yoshihiro Hirota ,  Kinji Yamada ,  Tomotaka Shinoda ,  Katsuya Okumura ,  Shuichi Kawano

Inventor： Yoshiki Yamanishi ,  Muneo Harada ,  Takahiro Kitano ,  Tatsuzo Kawaguchi ,  Yoshihiro Hirota ,  Kinji Yamada ,  Tomotaka Shinoda ,  Katsuya Okumura ,  Shuichi Kawano

IPC: H01L29/94

CPC classification number: H01L23/50 ,  H01G4/228 ,  H01G4/33 ,  H01L23/481 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/162 ,  H05K3/002 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/10378

Abstract: A capacitor having a high quality and a manufacturing method of the same are provided. A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.

Abstract translation: 提供了具有高质量的电容器及其制造方法。 电容器具有形成在氧化膜上的下电极，形成在下电极上的电介质层，形成为与电极之间介电层相对的下电极的上电极和形成为覆盖上电极的上电极 ，上电极的开口部分和电介质层的开口部分。 通过在电介质层上形成上电极，可以通过使用上电极作为掩模对电介质层进行图案化，并且通过防止杂质扩散到电介质层中来提供具有高质量电介质层的电容器。 通过在电介质层上形成上部电极，可以防止电介质层暴露于蚀刻液体，液体显影剂等

公开(公告)号：US20070164349A1

公开(公告)日：2007-07-19

申请号：US11616182

申请日：2006-12-26

Applicant: Mayumi Nakasato ,  Makoto Murai ,  Ryosuke Usui ,  Hideki Mizuhara ,  Yasunori Inoue

Inventor： Mayumi Nakasato ,  Makoto Murai ,  Ryosuke Usui ,  Hideki Mizuhara ,  Yasunori Inoue

IPC: H01L29/788

CPC classification number: H01L21/6835 ,  H01L23/145 ,  H01L23/3737 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0206 ,  H05K1/0373 ,  H05K3/421 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0209 ,  H05K2201/0248 ,  H05K2201/0266 ,  H05K2201/09509 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A circuit board includes a substrate and an insulating layer. The substrate has a first surface. The insulating layer has a second surface and is connected to the substrate. The first surface is in contact with the second surface. Heat-conductive particles are provided in the insulating layer. A part of the particles projects from the second surface of the insulating layer and is in contact with the first surface of the substrate.

Abstract translation: 电路板包括基板和绝缘层。 衬底具有第一表面。 绝缘层具有第二表面并连接到基板。 第一表面与第二表面接触。 在绝缘层中设置导热粒子。 一部分颗粒从绝缘层的第二表面突出并且与衬底的第一表面接触。

公开(公告)号：US20070143994A1

公开(公告)日：2007-06-28

申请号：US11681964

申请日：2007-03-05

Applicant: Anthony Primavera ,  Steven Findell

Inventor： Anthony Primavera ,  Steven Findell

IPC: H01L21/331

CPC classification number: H05K1/0271 ,  H05K1/0201 ,  H05K1/0269 ,  H05K1/0272 ,  H05K1/115 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0394 ,  H05K2201/062 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09509 ,  H05K2203/161 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204

Abstract: This document discusses, among other things, a flexible circuit or other laminate comprising a first conductive layer and a second conductive layer disposed over the first conductive layer. An insulator is disposed between the first and second conductive layers. A conductive via extends through the insulator and electrically connects the first and second conductive layers. The laminate includes a channel in the insulator. In one option, the channel extends at least part way around the via. In another option, the channel extends at least part way between the first and second conductive layers. In another example, a method comprises providing a laminate including at least first and second conductive layers and an insulator disposed therebetween. A via is formed through the insulator. A channel is formed in the insulator at least part way around the via. The channel extends between the first and second conductive layers.

Abstract translation: 本文件尤其涉及柔性电路或其它层压体，其包括设置在第一导电层上的第一导电层和第二导电层。 绝缘体设置在第一和第二导电层之间。 导电通孔延伸穿过绝缘体并电连接第一和第二导电层。 层压板包括绝缘体中的通道。 在一个选项中，通道至少部分地围绕通道延伸。 在另一选择中，通道至少部分地在第一和第二导电层之间延伸。 在另一示例中，一种方法包括提供包括至少第一和第二导电层以及设置在其间的绝缘体的层压体。 通孔通过绝缘体形成。 在绝缘体中至少部分地围绕通孔形成通道。 通道在第一和第二导电层之间延伸。

公开(公告)号：US20070141759A1

公开(公告)日：2007-06-21

申请号：US11612419

申请日：2006-12-18

Applicant: Kenji Nagase ,  Kenichi Kawabata

Inventor： Kenji Nagase ,  Kenichi Kawabata

IPC: H01L21/00

CPC classification number: H01L25/16 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K1/185 ,  H05K3/0044 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/10674 ,  H05K2203/025 ,  H05K2203/0554 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49151 ,  Y10T29/49155

Abstract: A method for manufacturing an IC-embedded substrate comprises a first step for encapsulating at least an IC chip having a pad electrode in an insulating layer, a second step for forming a metal layer having at least a first aperture in a location directly above the pad electrode of the IC chip and a second aperture in a location above an area other than the area in which the IC chip is mounted, and a third step for selectively removing the insulating layer by a blasting treatment in which the metal layer is used as a mask, whereby forming a first via hole that corresponds to the first aperture and a second via hole that corresponds to the second aperture.

Abstract translation: 一种用于制造嵌入IC的衬底的方法包括：第一步骤，用于将至少具有焊盘电极的IC芯片封装在绝缘层中;第二步骤，用于形成金属层，所述金属层至少具有位于衬垫上方的位置的第一孔 IC芯片的电极和除了安装IC芯片的区域之外的区域上方的位置的第二孔，以及第三步骤，通过其中使用金属层的喷砂处理来选择性地去除绝缘层， 从而形成对应于第一孔的第一通孔和对应于第二孔的第二通孔。

公开(公告)号：US20070132063A1

公开(公告)日：2007-06-14

申请号：US11304649

申请日：2005-12-14

Applicant: Yongki Min ,  John Guzek

Inventor： Yongki Min ,  John Guzek

IPC: H01L29/00

CPC classification number: H05K1/162 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/10674

Abstract: In an embodiment, a substrate includes a thin film capacitor embedded within. In an embodiment, a plurality of adhesion holes extend through the thin film capacitor. These adhesion holes may improve the adhesion of the capacitor to other portions of the substrate.

Abstract translation: 在一个实施例中，衬底包括嵌入其中的薄膜电容器。 在一个实施例中，多个粘附孔延伸穿过薄膜电容器。 这些粘附孔可以改善电容器与基片的其它部分的粘合性。

公开(公告)号：US20070130761A1

公开(公告)日：2007-06-14

申请号：US11591586

申请日：2006-11-02

Applicant: Myung Kang ,  Shuhichi Okabe ,  Jung Park ,  Hoe Jung ,  Ji Kim

Inventor： Myung Kang ,  Shuhichi Okabe ,  Jung Park ,  Hoe Jung ,  Ji Kim

IPC: H05K1/11

CPC classification number: H05K1/116 ,  H05K3/0094 ,  H05K3/421 ,  H05K3/428 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2203/0361 ,  H05K2203/0384 ,  H05K2203/0542 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49133 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Disclosed is a method of manufacturing a printed circuit board having a landless via hole. Specifically, this invention provides a method of manufacturing a printed circuit board having a landless via hole without the upper land of a via hole using a photoresist (P-LPR) which is loaded in the via hole. Therefore, in this invention, since a circuit pattern is formed using only copper of a copper clad laminate, the width thereof is minimized, thus easily realizing a fine circuit pattern. Further, the landless via hole structure is applied, resulting in a highly dense circuit pattern.

Abstract translation: 公开了一种具有无地过孔的印刷电路板的制造方法。 具体而言，本发明提供一种制造印刷电路板的方法，所述印刷电路板具有无通孔通孔，所述无通孔通孔使用装载在所述通孔中的光致抗蚀剂（P-LPR）而不具有通孔的上部焊盘。 因此，在本发明中，由于仅使用覆铜层压板的铜形成电路图案，所以其宽度被最小化，因此容易实现精细电路图案。 此外，施加无地通孔结构，导致高度密集的电路图案。

公开(公告)号：US07219845B2

公开(公告)日：2007-05-22

申请号：US10969861

申请日：2004-10-22

Applicant: Noboru Nishida

Inventor： Noboru Nishida

IPC: G06K19/06

CPC classification number: H05K1/117 ,  H05K1/0298 ,  H05K2201/09481 ,  H05K2201/09509

Abstract: A card-type electronic device has a multilayer printed wiring board and a case which houses the multilayer printed wiring board. The case has an opening. The multilayer printed wiring board includes a plurality of insulating layers and a plurality of conductive layers, which are alternately stacked, and has a flat surface on one side thereof along a stacked direction. The flat surface is formed of one of the insulating layers, and at least a part of the flat surface is exposed to the outside of the case through the opening.

Abstract translation: 卡式电子设备具有多层印刷线路板和容纳多层印刷线路板的壳体。 案件有一个开场。 多层印刷线路板包括交替堆叠的多个绝缘层和多个导电层，并且沿堆叠方向在其一侧具有平坦表面。 平坦表面由绝缘层之一形成，并且平坦表面的至少一部分通过开口暴露于外壳的外部。

公开(公告)号：US20070108619A1

公开(公告)日：2007-05-17

申请号：US11274016

申请日：2005-11-15

Applicant: Jun Hsu

Inventor： Jun Hsu

IPC: H01L29/40

CPC classification number: H05K1/112 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H05K1/116 ,  H05K3/244 ,  H05K3/421 ,  H05K2201/09436 ,  H05K2201/09463 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09663 ,  H01L2924/00

Abstract: A bonding pad with high bonding strength to a solder ball and a bump includes a carrier, a wiring layer formed on the carrier, a protection layer formed on top of the wiring layer and a solder mask layer surrounded around the protection layer and the wiring layer to form a bonding pad opening. The protection layer is extended outside the bonding pad opening such that when solder are extended into the bonding pad opening, the solder balls engage with side faces defining the bump pad opening as well as the protection layer outside the bump pad opening and a bonding strength between the bonding pad and the solder performance is increased.

Abstract translation: 具有对焊球和凸块具有高结合强度的接合焊盘包括载体，形成在载体上的布线层，形成在布线层顶部的保护层和围绕保护层和布线层围绕的焊料掩模层 以形成接合焊盘开口。 保护层延伸到接合焊盘开口的外部，使得当焊料延伸到焊盘开口中时，焊球与限定凸块焊盘开口的侧面以及凸块焊盘开口之外的保护层接合， 焊盘和焊料性能提高。

公开(公告)号：US20070108572A1

公开(公告)日：2007-05-17

申请号：US11410986

申请日：2006-04-26

Applicant: Yung-Yu Hsu ,  Rong-Chang Feng ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Ji-Cheng Lin ,  Shan-Pu Yu ,  Shou-Lung Chen ,  Chih-Yuah Cheng

Inventor： Yung-Yu Hsu ,  Rong-Chang Feng ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Ji-Cheng Lin ,  Shan-Pu Yu ,  Shou-Lung Chen ,  Chih-Yuah Cheng

IPC: H01L21/00

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/4644 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2201/09909 ,  H01L2924/00

Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.

Abstract translation: 提供一种用于减小通孔应力的结构及其制造方法。 使用栅格结构中的应力块与绝缘材料的主要部分直接接触，具有高的热膨胀系数，使厚度方向上的一个或多个导线或通孔被固定。 因此，由温度加载引起的剪切应力可以被应力块阻挡或吸收。