公开(公告)号：US20070086145A1

公开(公告)日：2007-04-19

申请号：US11546889

申请日：2006-10-13

Applicant: Kazuyuki Kubota ,  Tomoharu Fujii

Inventor： Kazuyuki Kubota ,  Tomoharu Fujii

IPC: H01G4/06

CPC classification number: H05K1/186 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/162 ,  H05K3/002 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09909 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: A capacitor-built-in substrate of the present invention contains a capacitor which includes a lower common electrode, a plurality of dielectric portions formed on the lower common electrode to be isolated mutually and coupled electrically to the lower common electrode, an insulating layer formed between the plurality of dielectric portions and on a surrounding area, and an upper common electrode formed on the plurality of dielectric portions and the insulating layer, and coupled electrically to the plurality of dielectric portions.

Abstract translation: 本发明的电容器内置基板包括电容器，该电容器包括下公共电极，形成在下公共电极上的多个电介质部分，用于互相隔离并与下公共电极电连接;绝缘层， 所述多个电介质部分和周围区域，以及形成在所述多个电介质部分和所述绝缘层上的上部公共电极，并且电耦合到所述多个电介质部分。

公开(公告)号：US07205668B2

公开(公告)日：2007-04-17

申请号：US11285334

申请日：2005-11-22

Applicant: Ching-Yuan Wu ,  Kuang-Jen Liu ,  Chun-Chi Hsu

Inventor： Ching-Yuan Wu ,  Kuang-Jen Liu ,  Chun-Chi Hsu

IPC: H01L23/04 ,  H01L23/02 ,  H05K7/06

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/429 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09836

Abstract: A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle layer and the second wire layer. The manufacturing method includes the steps of providing a first wire layer and forming a first wiring on the first wire layer, forming a middle layer on the first wire layer, forming a second wire layer on the middle layer, forming a slanting via in the middle layer and the second wire layer wherein the direction of the slanting via is not orthogonal to the first and the second wire layers, forming a second wiring on the second wire layer by an etching method, and forming an electroplated layer in the via to connect the first wiring and the second wiring.

Abstract translation: 多层印刷电路板（PCB）包括第一布线层，第一布线层之上的中间层，中间层上方的第二布线层和形成在中间层和第二布线层中的倾斜孔。 该制造方法包括以下步骤：在第一布线层上形成第一布线层并形成第一布线，在第一布线层上形成中间层，在中间层上形成第二布线层，在中间层形成倾斜孔 层和第二线层，其中倾斜通孔的方向不与第一和第二线层正交，通过蚀刻方法在第二线层上形成第二布线，并且在通孔中形成电镀层以连接 第一布线和第二布线。

公开(公告)号：US07205486B2

公开(公告)日：2007-04-17

申请号：US10892648

申请日：2004-07-16

Applicant: Anthony Primavera ,  Steven P. Findell

Inventor： Anthony Primavera ,  Steven P. Findell

IPC: H01L23/48

CPC classification number: H05K1/0271 ,  H05K1/0201 ,  H05K1/0269 ,  H05K1/0272 ,  H05K1/115 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0394 ,  H05K2201/062 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09509 ,  H05K2203/161 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204

Abstract: This document discusses, among other things, a flexible circuit or other laminate comprising a first conductive layer and a second conductive layer disposed over the first conductive layer. An insulator is disposed between the first and second conductive layers. A conductive via extends through the insulator and electrically connects the first and second conductive layers. The laminate includes a channel in the insulator. In one option, the channel extends at least part way around the via. In another option, the channel extends at least part way between the first and second conductive layers. In another example, a method comprises providing a laminate including at least first and second conductive layers and an insulator disposed therebetween. A via is formed through the insulator. A channel is formed in the insulator at least part way around the via. The channel extends between the first and second conductive layers.

Abstract translation: 本文件尤其涉及柔性电路或其它层压体，其包括设置在第一导电层上的第一导电层和第二导电层。 绝缘体设置在第一和第二导电层之间。 导电通孔延伸穿过绝缘体并电连接第一和第二导电层。 层压板包括绝缘体中的通道。 在一个选项中，通道至少部分地围绕通道延伸。 在另一选择中，通道至少部分地在第一和第二导电层之间延伸。 在另一示例中，一种方法包括提供包括至少第一和第二导电层以及设置在其间的绝缘体的层压体。 通孔通过绝缘体形成。 在绝缘体中至少部分地围绕通孔形成通道。 通道在第一和第二导电层之间延伸。

公开(公告)号：US07193838B2

公开(公告)日：2007-03-20

申请号：US10744695

申请日：2003-12-23

Applicant: Gregory J. Dunn ,  Remy J. Chilini ,  Robert T. Croswell ,  Timothy B. Dean ,  Claudia V. Gamboa ,  Jovica Savic

Inventor： Gregory J. Dunn ,  Remy J. Chilini ,  Robert T. Croswell ,  Timothy B. Dean ,  Claudia V. Gamboa ,  Jovica Savic

IPC: H01G4/30

CPC classification number: H05K1/162 ,  H05K3/025 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

Abstract: A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (>1000 pf/mm2).

Abstract translation: 电介质电路板箔（400,600）包括导电金属箔层（210,660），邻近导电金属箔层的第一表面设置的结晶介电氧化物层（405,655），镍酸镧层（414） ，664）和基本上由设置在镍酸镧层上的一种或多种贱金属制成的电极层（415,665）。 箔（400,600）可以粘附到印刷电路板子结构（700）上，并用于经济地制造多个嵌入式电容器，包括具有大电容密度（> 1000pf / mm 2）的隔离电容器， / SUP>）。

公开(公告)号：US20070054420A1

公开(公告)日：2007-03-08

申请号：US11220131

申请日：2005-09-06

Applicant: Chee Lu ,  Boon Lok

Inventor： Chee Lu ,  Boon Lok

IPC: H01L21/00

CPC classification number: H05K1/162 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09509

Abstract: A substrate structure and method of wideband power decoupling comprising one or more embedded capacitors each comprising a ferroelectric material.

Abstract translation: 宽带功率去耦的衬底结构和方法，包括一个或多个嵌入式电容器，每个包含铁电材料。

公开(公告)号：US20070010065A1

公开(公告)日：2007-01-11

申请号：US11352279

申请日：2006-02-13

Applicant: Rabindra Das ,  John Lauffer ,  How Lin ,  Voya Markovich

Inventor： Rabindra Das ,  John Lauffer ,  How Lin ,  Voya Markovich

IPC: H01L21/20 ,  H01L21/44

CPC classification number: H05K1/162 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2203/013 ,  H05K2203/0568

Abstract: A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate. The capacitive substrate may be incorporated within a larger circuitized substrate, e.g., to form an electrical assembly. A method of making an information handling system including such substrates is also provided.

Abstract translation: 一种形成电容衬底的方法，其中材料的至少一个电容介电层被屏幕或喷墨印刷到导体上，然后进一步处理衬底，包括添加通孔以将所选择的元件耦合到衬底内以形成 至少两个电容器作为衬底的内部元件。 电容性衬底可以结合在更大的电路化衬底内，例如以形成电组件。 还提供了一种制造包括这种基板的信息处理系统的方法。

公开(公告)号：US20070007034A1

公开(公告)日：2007-01-11

申请号：US11474921

申请日：2006-06-26

Applicant: Arash Behziz ,  Roya Yaghmai

Inventor： Arash Behziz ,  Roya Yaghmai

IPC: H05K1/11 ,  H05K3/42

CPC classification number: H05K1/115 ,  G01R31/2889 ,  H05K3/3421 ,  H05K3/4602 ,  H05K2201/049 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09627 ,  H05K2201/10189 ,  Y10T29/49165

Abstract: In one embodiment, a laminated printed circuit board translator is provided. In some embodiments, the translator includes a receiving board adapted to receive a pin, the receiving board includes a plated via extending through the receiving board and has a hole for receiving a pin. An interface board laminated with the receiving board has a controlled depth via extending through it to contact a conductive trace. The conductive trace extends between the receiving board and the interface board to connect the plated via of the receiving board with the controlled depth via of the interface board. The controlled depth via is configured so that it is capable of being plated through a single sided drilled opening in the interface board. Some embodiments have a pad on the interface board connected to the controlled depth via.

Abstract translation: 在一个实施例中，提供了层压印刷电路板转换器。 在一些实施例中，翻译器包括适于接收销的接收板，接收板包括延伸穿过接收板的电镀通孔，并具有用于接收销的孔。 与接收板层压的接口板具有通过其延伸的受控深度以接触导电迹线。 导电迹线在接收板和接口板之间延伸，以将接收板的电镀通孔与接口板的受控深度通孔连接。 受控深度通孔被配置成能够通过接口板中的单面钻孔而进行电镀。 一些实施例在接口板上具有连接到受控深度通孔的垫。

公开(公告)号：US20070000691A1

公开(公告)日：2007-01-04

申请号：US11478922

申请日：2006-06-30

Applicant: Yu-Hsu Lin ,  Shang-Tsang Yeh ,  Chao-Chen Huang ,  Chuan-Bing Li

Inventor： Yu-Hsu Lin ,  Shang-Tsang Yeh ,  Chao-Chen Huang ,  Chuan-Bing Li

IPC: H05K1/11

CPC classification number: H05K1/116 ,  H05K1/0216 ,  H05K3/429 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09718 ,  Y10T29/49165

Abstract: A printed circuit board (PCB) having vias for reducing reflections of input signals includes a first signal layer, a second signal layer, one via, an input signal line arranged on the first signal layer, and an output signal line arranged on the second signal layer. The via further includes a drill hole, a first pad, and a second pad. The first pad is electrically connected with the input signal line, and the second pad is electrically connected with the output signal line. An outer diameter of the first pad is smaller than an outer diameter of the second pad.

Abstract translation: 具有用于减少输入信号的反射的通孔的印刷电路板（PCB）包括第一信号层，第二信号层，一个通孔，布置在第一信号层上的输入信号线和布置在第二信号上的输出信号线 层。 通孔还包括钻孔，第一垫和第二垫。 第一焊盘与输入信号线电连接，第二焊盘与输出信号线电连接。 第一垫的外径小于第二垫的外径。

公开(公告)号：US07145231B2

公开(公告)日：2006-12-05

申请号：US10844392

申请日：2004-05-13

Applicant: Takehiko Hasebe ,  Takehide Yokozuka ,  Nobuyuki Ushifusa ,  Masahide Harada ,  Eiji Matsuzaki ,  Hiroshi Hozoji

Inventor： Takehiko Hasebe ,  Takehide Yokozuka ,  Nobuyuki Ushifusa ,  Masahide Harada ,  Eiji Matsuzaki ,  Hiroshi Hozoji

IPC: H01L23/34

CPC classification number: H01L24/16 ,  H01L23/142 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/32057 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/83851 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01054 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/021 ,  H05K1/056 ,  H05K1/144 ,  H05K3/384 ,  H05K3/4608 ,  H05K3/4641 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10734 ,  H01L2924/05432 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides an electronic apparatus having a metal core substrate including a metal plate, an insulating layer formed on the metal plate and a conductive layer formed on the insulating layer, and an electronic part, and to which the conductive layer and a terminal of the electronic part are connected. In the electronic apparatus, a member having a high thermal conductivity is arranged so as to be in contact with both of the metal plate and the electronic part. Accordingly, a heat radiating property of the electronic apparatus is increased.

公开(公告)号：US20060254810A1

公开(公告)日：2006-11-16

申请号：US11488799

申请日：2006-07-19

Applicant: Herman Kwong ,  Luigi Difilippo ,  Guy Duxbury ,  Larry Marcanti

Inventor： Herman Kwong ,  Luigi Difilippo ,  Guy Duxbury ,  Larry Marcanti

IPC: H05K1/03 ,  H05K1/11

CPC classification number: H05K1/112 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A technique for accommodating electronic components on a multilayer signal routing device is disclosed. In one particular exemplary embodiment, the technique may be realized as a multilayer signal routing device comprising a primary surface and a secondary surface. The primary surface may have a plurality of electrically conductive pads formed thereon, wherein a group of the plurality of electrically conductive pads is in respective electrical connection with a group of electrically conductive micro-vias formed in the multilayer signal routing device. The secondary surface may have a channel formed thereon coinciding with the location of the group of electrically conductive micro-vias, wherein the channel has a channel area on the secondary surface for accommodating an electronic component mounted on the secondary surface.

Abstract translation: 公开了一种用于在多层信号路由设备上容纳电子部件的技术。 在一个特定的示例性实施例中，该技术可以被实现为包括主表面和次表面的多层信号路由设备。 主表面可以具有形成在其上的多个导电焊盘，其中一组多个导电焊盘与形成在多层信号路由装置中的一组导电微通孔分别电连接。 次表面可以具有与导电微通孔组的位置重合的通道，其中通道在次表面上具有用于容纳安装在次表面上的电子部件的通道区域。