公开(公告)号：US06700748B1

公开(公告)日：2004-03-02

申请号：US09561821

申请日：2000-04-28

Applicant: Kevin Cowles ,  A. David Erpelding

Inventor： Kevin Cowles ,  A. David Erpelding

IPC: G11B540

CPC classification number: G11B5/486 ,  G11B5/02 ,  G11B5/11 ,  G11B5/112 ,  G11B5/3143 ,  G11B5/40 ,  G11B2005/0016 ,  H05K1/0215 ,  H05K3/4069 ,  H05K3/4084 ,  H05K3/44 ,  H05K2201/0305 ,  H05K2201/09554 ,  Y10T29/4903 ,  Y10T29/49032 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49165 ,  Y10T29/49179 ,  Y10T29/49224

Abstract: In an Integrated Lead Suspension system, it is desired that the stainless steel suspension is grounded to a controlled ground potential. This requires creating a grounding path between the stainless steel suspension and a copper trace layer through a layer of dielectric material that separates the stainless steel suspension and the copper layer. The copper trace layer and subsequently the stainless steel suspension can then be grounded to a controlled ground potential. This invention proposes several methods of creating a ground path between the stainless steel suspension and the copper trace layer.

Abstract translation: 在集成式悬挂系统中，希望不锈钢悬架接地到受控的接地电位。 这需要通过分离不锈钢悬浮液和铜层的介电材料层在不锈钢悬浮液和铜迹线层之间形成接地路径。 然后将铜迹线层和随后的不锈钢悬浮液接地到受控的接地电位。本发明提出了在不锈钢悬浮液和铜迹线层之间产生接地路径的几种方法。

公开(公告)号：US06681483B2

公开(公告)日：2004-01-27

申请号：US10125221

申请日：2002-04-18

Applicant: E. James Crescenzi, Jr. ,  Anwar A. Mohammed

Inventor： E. James Crescenzi, Jr. ,  Anwar A. Mohammed

IPC: H01K310

CPC classification number: H05K3/44 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0047 ,  H05K3/0061 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09554 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/171 ,  H05K2203/175 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed circuit architecture includes a relatively thick, stiffening base of thermally and electrically conductive material, and a laminate of conductive layers including a printed circuit structure, interleaved with dielectric layers, disposed atop the base. The patterned conductive layers contain an integrated circuit structure that is configured to provide RF signaling, microstrip shielding, and digital and analog control signal leads, and DC power. Low inductance electrical connectivity among the conductive layers and also between conductive layers and the base is provided by a plurality of conductive bores. Selected bores are counter-drilled at the RF signaling layer and filled with insulating plugs, which prevent shorting of the RF signal trace layer to ground, during solder reflow connection of leads of circuit components to the RF signaling layer.

Abstract translation: 印刷电路架构包括相对厚的加热和导电材料的加强基底，以及布置在基底顶部的包括与电介质层交织的印刷电路结构的导电层的层压体。 图案化导电层包含被配置为提供RF信号，微带屏蔽以及数字和模拟控制信号引线以及DC电力的集成电路结构。 导电层之间以及导电层和基底之间的低电感电连接由多个导电孔提供。 选择的孔在RF信号层反相钻孔，并填充有绝缘插头，以防止将RF信号迹线层短路到地，将电路部件的引线与RF信号层焊接回流连接。

公开(公告)号：US20040000049A1

公开(公告)日：2004-01-01

申请号：US10184192

申请日：2002-06-27

Inventor： Gregory J. McCollum ,  Thomas C. Moriarity ,  Kevin C. Olson ,  Michael G. Sandala ,  Alan E. Wang ,  Steven R. Zawacky

IPC: H01K003/10 ,  H05K003/02

CPC classification number: H05K3/44 ,  H01L2924/0002 ,  H05K1/056 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/445 ,  H05K2201/09554 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Provided is a process for forming metallized vias in a substrate including the steps of (I) applying to an electroconductive substrate an electrodepositable coating composition onto all exposed surfaces of the substrate to form a conformal dielectric coating; (II) ablating a surface of the dielectric coating to expose a section of the substrate; (III) applying a layer of metal to all surfaces to form metallized vias in the substrate. Also disclosed are processes for fabricating a circuit assembly which include the application of an electrodoepositable coating composition onto exposed surfaces of the substrate/core to form a conformal dielectric coating thereon. The electrodepositable coating composition includes a resinous phase dispersed in an aqueous phase, where the resinous phase has a covalently bonded halogen content of at least 1 percent by weight. The dielectric coating derived therefrom has a low dielectric constant and low dielectric loss factor.

Abstract translation: 提供了一种用于在基底中形成金属化通孔的方法，包括以下步骤：（I）将可电沉积涂料组合物施加到导电基底上，以在基底的所有暴露表面上形成共形绝缘涂层; （II）烧蚀所述电介质涂层的表面以暴露所述衬底的一部分; （III）将金属层施加到所有表面以在基底中形成金属化通孔。 还公开了用于制造电路组件的方法，其包括将电沉积涂料组合物施加到基材/芯的暴露表面上以在其上形成共形绝缘涂层。 电沉积涂料组合物包括分散在水相中的树脂相，其中树脂相具有至少1重量％的共价键合的卤素含量。 由此得到的电介质涂层具有低介电常数和低介电损耗因子。

公开(公告)号：US20030234117A1

公开(公告)日：2003-12-25

申请号：US10179066

申请日：2002-06-25

Inventor： Lawrence R. Poglitsch ,  Ronald Li ,  Alan S. Kang ,  Todd Ringa ,  Steven G. Sharkey ,  Rick Cihak

IPC: H05K001/11

CPC classification number: H05K3/363 ,  H01R13/58 ,  H01R43/0256 ,  H05K1/0215 ,  H05K1/0271 ,  H05K3/0061 ,  H05K3/4038 ,  H05K3/44 ,  H05K2201/0305 ,  H05K2201/09063 ,  H05K2201/09554

Abstract: A ground connector assembly (20) having a substrate (22) and a ground member (24). The substrate (22) is used to retain an electrical circuit and has a ground region (34), a ground hole (30), and at least one strain relief slot (32). The ground member (24) is attached within the ground hole (30). The ground region (34) surrounds the ground hole (30) and is at least partially interposed between the ground hole (30) and the strain relief slot (32). The ground connector assembly (20) may further include a conductive ring (42), such as a copper ring, surrounding the ground hole (30) and attached to the ground region (34). There is also a method of making the ground connector assembly (20).

Abstract translation: 一种具有衬底（22）和接地构件（24）的接地连接器组件（20）。 衬底（22）用于保持电路并具有接地区域（34），接地孔（30）和至少一个应变消除槽（32）。 接地构件（24）附接在接地孔（30）内。 接地区域34围绕着接地孔30并且至少部分地插入在接地孔30和应变消除槽32之间。 接地连接器组件（20）还可以包括围绕接地孔（30）并连接到接地区域（34）的导电环（42），例如铜环。 还有一种制造接地连接器组件（20）的方法。

公开(公告)号：US20030215619A1

公开(公告)日：2003-11-20

申请号：US10436143

申请日：2003-05-13

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kazuhiko Ooi ,  Masaru Yamazaki ,  Yukiji Watanabe ,  Takaaki Yazawa

IPC: B32B015/04

CPC classification number: H05K3/44 ,  H05K3/429 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09518 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09718 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09845 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A metal core substrate comprises a core layer (10) consisting of first and second metal plates (11, 12) layered with a third insulating layer (13) interposed therebetween; first and second insulating layers (20, 21) formed on the first and metal plates, respectively; first and second wiring patterns (45, 46) formed on the first and second insulating layers, respectively. A conductive layer (40) formed in a through-hole (22) penetrates the first insulating layer, the first metal plate, the third insulating layer, the second metal plate and the second insulating layer for electrically connecting the first wiring pattern with the second wiring pattern. The first metal plate (11) is electrically connected with the first wiring pattern (45) and the second wiring pattern (46), respectively, by means of a via (44) and by means a via (43). The second metal plate (12) is electrically connected with the second wiring pattern (46) and the first wiring pattern (45), respectively, by means of a via (42) and by means a via (41), respectively.

Abstract translation: 金属芯基板包括由第一和第二金属板（11,12）组成的芯层（10），第一和第二金属板与第三绝缘层（13）分开; 分别形成在第一和金属板上的第一和第二绝缘层（20,21）; 分别形成在第一和第二绝缘层上的第一和第二布线图案（45,46）。 形成在通孔（22）中的导电层（40）穿过第一绝缘层，第一金属板，第三绝缘层，第二金属板和第二绝缘层，用于将第一布线图案与第二绝缘层 接线图案。 第一金属板（11）通过通孔（44）和通孔（43）分别与第一布线图案（45）和第二布线图案（46）电连接。 第二金属板（12）分别通过通孔（42）和通孔（41）与第二布线图案（46）和第一布线图案（45）电连接。

公开(公告)号：US20030213767A1

公开(公告)日：2003-11-20

申请号：US10426326

申请日：2003-04-29

Inventor： Robert Edward Belke JR. ,  Vivek A. Jairazbhoy ,  Thomas B. Krautheim ,  William F. Quitty JR.

IPC: H01B013/00

CPC classification number: H05K3/44 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0361 ,  H05K2201/09554 ,  H05K2201/09745 ,  H05K2201/0979 ,  H05K2201/09854 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49156

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26 which have improved solder-wetting characteristics.

Abstract translation: 具有选择性地形成的具有改善的焊料润湿特性的孔或腔26的多层电子电路板设计10。

公开(公告)号：US06623651B2

公开(公告)日：2003-09-23

申请号：US09815364

申请日：2001-03-22

Applicant: Bharat Patel ,  Jay D. Baker ,  Mohan Paruchuri

Inventor： Bharat Patel ,  Jay D. Baker ,  Mohan Paruchuri

IPC: H01B1300

CPC classification number: H05K3/44 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4647 ,  H05K3/4652 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536

Abstract: A method 10 for making a multi-layer electronic circuit board 98 having at least one electrically conductive protuberance 15 which forms a “via” and which traverses through the various layers of the electric circuit board 98, and further having at least one interconnection portion 102 which supports a wide variety of components and interconnection assemblies.

Abstract translation: 一种用于制造多层电子电路板98的方法10，该多层电子电路板98具有形成“通孔”的至少一个导电突起15，并穿过电路板98的各个层，并且还具有至少一个互连部分102 其支持各种组件和互连组件。

公开(公告)号：US20030140490A1

公开(公告)日：2003-07-31

申请号：US10291876

申请日：2002-11-08

Inventor： Kevin C. Olson ,  Alan E. Wang

IPC: H05K003/36

CPC classification number: C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.

Abstract translation: 提供了用于制造多层电路组件的工艺和通过这些工艺制造的多层电路组件。 该方法包括（a）提供基底，其至少一个区域包括多个通孔，这些区域的通孔密度为500至10,000个孔/平方英寸（75至1550个孔/平方厘米）; （b）将介电涂层施加到所述基底的所有暴露表面上以在其上形成保形涂层; 和（c）在基片的所有表面上涂一层金属。 可以包括诸如电路化的附加处理步骤。

公开(公告)号：US06579565B2

公开(公告)日：2003-06-17

申请号：US10184968

申请日：2002-07-01

Applicant: Kinji Saijo ,  Shinji Ohsawa ,  Kazuo Yoshida

Inventor： Kinji Saijo ,  Shinji Ohsawa ,  Kazuo Yoshida

IPC: B05D512

CPC classification number: H05K3/062 ,  H05K3/20 ,  H05K3/44 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/09554 ,  H05K2203/0384 ,  H05K2203/0733 ,  Y10S428/901 ,  Y10T428/12903 ,  Y10T428/1291 ,  Y10T428/12931 ,  Y10T428/12944 ,  Y10T428/24917

Abstract: A multilayered circuit board is produced by: a. laminating a copper foil conductor layer and a nickel foil or nickel plating etch-stopping layer by simultaneously press-bonding the nickel and copper layer to form a multilayered clad sheet; b. selectively etching the multilayered clad sheet; c. forming an insulating layer and an outer conductor layer on the surface of the clad sheet; d. patterning the outer conductor layer; and e. electrically connecting the internal conductor layer and the outer conductor layer by interposing a columnar conductor formed in the base by etching.

Abstract translation: 多层电路板由以下产品制成：a。 通过同时压合镍和铜层来层压铜箔导体层和镍箔或镍电镀蚀刻停止层以形成多层包覆片; b。 选择性地蚀刻多层复合板; c。 在包覆板的表面上形成绝缘层和外导体层; d。 图案化外导体层; 安德 通过蚀刻形成在基底中的柱状导体来电连接内导体层和外导体层。

公开(公告)号：US20030058630A1

公开(公告)日：2003-03-27

申请号：US10244210

申请日：2002-09-16

Inventor： Akihito Takano ,  Takahiro Iijima

IPC: H05K007/02 ,  H05K007/06 ,  H05K007/08 ,  H05K007/10

CPC classification number: H05K1/0206 ,  H01L23/10 ,  H01L23/36 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K3/44 ,  H05K3/4608 ,  H05K2201/09554 ,  H05K2201/096

Abstract: A multilayer circuit board for mounting a semiconductor element thereon, comprising a core substrate of a metal material and a plurality of wiring layers stacked on either side of the core substrate, each of the stacked wiring layers being isolated from an adjacent wiring layer by an insulating layer interposed therebetween, the multilayer circuit board having an area at which a heat spreader for dissipating heat generated from the semiconductor element mounted on the circuit board is to be joined to the multilayer circuit board, wherein the multilayer circuit board allows the heat spreader to be joined to the core substrate without the insulating layers being interposed therebetween. A semiconductor device using the multilayer circuit board is also disclosed.

Abstract translation: 一种用于在其上安装半导体元件的多层电路板，包括金属材料的芯基板和堆叠在芯基板的两侧的多个布线层，每个堆叠的布线层通过绝缘体与相邻布线层隔离 层叠电路板，其中，多层电路板具有用于散热从安装在电路板上的半导体元件产生的散热器的散热器与多层电路板接合的区域，其中多层电路板允许散热器为 连接到芯基板上，绝缘层之间插入其中。 还公开了一种使用该多层电路板的半导体器件。